Kenneth L Chaney

US Patent:

58813160, Mar 9, 1999

Filed:

Nov 12, 1996

Appl. No.:

8/748226

Inventors:

Kenneth Chaney - Plano TX
Michael T. Ruff - Allen TX

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1300

US Classification:

395876

Abstract:

The space of a buffer is logically partitioned into space reserved for requests only, space reserved for responses only, and space that can be used for either requests or responses, i. e. , dynamically usable as needed by the system. An arbiter uses three registers to keep track of the request buffer space, the response buffer space and the dynamic space. The arbiter compares each of the registers with a corresponding limit to determine if a request packet or a response packet should be sent to the buffer. The limits are set by software and define the maximum number of request products, response packets, and total number of packets the buffer can hold. For example, the limit may be set to eight requests, eight responses and ten total. Thus two spaces are reserved for requests and two spaces are reserved for responses, and six are dynamically usable.

US Patent:

60618191, May 9, 2000

Filed:

Dec 29, 1997

Appl. No.:

8/999099

Inventors:

Lionel Bening - Plano TX
Kenneth Chaney - Plano TX

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G01R 3128
G06F 1100

US Classification:

714741

Abstract:

The inventive mechanism generates reproducible random initial states for use in simulation testing a design of a logic machine. The mechanism uses the hierarchical path names for the modules of the design and a random seed to generate reproducible random initialization states. Since the path names and the seed are known quantities, the random number can be reproduced. This allows the logic designs to be tested by different simulation methods and still have the same initialization states. Furthermore, if the simulation fails, design changes can be verified by using the same initialization states which caused the failure.

US Patent:

59338571, Aug 3, 1999

Filed:

Apr 25, 1997

Appl. No.:

8/845306

Inventors:

Tony M. Brewer - Plano TX
Kenneth Chaney - Plano TX
Roger Sunshine - Plano TX

Assignee:

Hewlett-Packard Co. - Palo Alto CA

International Classification:

G06F 1200
G06F 1202
G06F 1210

US Classification:

711202

Abstract:

Microkernel memory references, traditionally required to refer to memory by exact physical address, are transformed so as to be able to map the references to addresses in multiple memory nodes. As a result, each node's address space may be compiled to by multiple microkernels. Reverse mapping responsive to coherency requests facilitates cache coherency.

US Patent:

59308222, Jul 27, 1999

Filed:

Sep 27, 1996

Appl. No.:

8/720330

Inventors:

Kenneth Chaney - Plano TX
David M. Chastain - Plano TX
David M. Patrick - Plano TX

Assignee:

Hewlett-Packard Co. - Palo Alto CA

International Classification:

G06F 1318

US Classification:

711150

Abstract:

A method and system of maintaining strong ordering in a multiprocessor computer system having a coherent memory. Memory transactions are send from one or more processors to a processor agent. The processor agent sends the transactions to a memory agent via a crossbar switch. The memory agent performs memory coherency operations and sends memory transactions back to the processor agents via the crossbar switch. The crossbar switch, however, may alter the order in which the memory transactions are forwarded to the processor agent. Therefore, the memory agent also sends a timestamp for each memory transaction directly to the processor agent via a dedicated link. An arbitrator within the processor agent receives the timestamps and the memory transactions. Using the timestamps, the arbitrator reorders the memory transactions and sends the transactions to the processors in the order in which the transactions were sent. In addition, the memory agent sends a parity signal with each timestamp.