Kenneth L Devries

US Patent:

7408206, Aug 5, 2008

Filed:

Nov 21, 2005

Appl. No.:

11/164377

Inventors:

Kenneth L. DeVries - Hopewell Junction NY, US
Nancy Anne Greco - LaGrangeville NY, US
Joan Preston - Wimberley TX, US
Stephen Larry Runyon - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/017

US Classification:

257127, 257170, 257409, 257452, 257484, 257605, 257E29012

Abstract:

Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

US Patent:

7759173, Jul 20, 2010

Filed:

Apr 15, 2008

Appl. No.:

12/103212

Inventors:

Kenneth L. DeVries - Hopewell Junction NY, US
Nancy Anne Greco - Lagrangeville NY, US
Joan Preston - Wimberley TX, US
Stephen Larry Runyon - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/332

US Classification:

438140, 438381, 257127, 257170

Abstract:

Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

US Patent:

20050242439, Nov 3, 2005

Filed:

Apr 28, 2004

Appl. No.:

10/709325

Inventors:

Kenneth DeVries - Hopewell Junction NY, US
Jeffrey Gambino - Westford VT, US
Stephen Luce - Underhill VT, US
James Warnock - Somers NY, US
Francis White - Essex VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L023/48

US Classification:

257758000

Abstract:

A structure (and method) for an electronic chip, includes a first circuit design module having a first grid and a second circuit design module having a second grid. The first grid and the second grid are interconnected in a fabrication layer no later than a first metallization layer that accumulates a charge during a plasma process in the fabrication.

US Patent:

51887045, Feb 23, 1993

Filed:

May 9, 1991

Appl. No.:

7/700871

Inventors:

Wayne T. Babie - Poughkeepsie NY
Kenneth L. Devries - Hopewell Junction NY
Bang C. Nguyen - Wappingers Falls NY
Chau-Hwa J. Yang - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B44C 122
C03C 1500
C03C 2506

US Classification:

156643

Abstract:

A two step method of etching a silicon nitride layer carrying a surface oxygen film from a substrate in a plasma reactor employs the steps of (1) a breakthrough step of employing a plasma of oxygen free etchant gases to break through and to remove the surface oxygen containing film from the surface of the silicon nitride layer, and (2) a main step of etching the newly exposed silicon nitride with etchant gases having high selectivity with respect to the silicon oxide underlying the silicon nitride. The plasma etching can be performed while employing magnetic-enhancement of the etching. The plasma etching is performed in a plasma reactor comprising a low pressure, single wafer tool. Plasma etching is performed while employing magnetic-enhancement of the etching. The etchant gases include a halide such as a bromide and a fluoride in the breakthrough step.

US Patent:

54317720, Jul 11, 1995

Filed:

Oct 19, 1992

Appl. No.:

7/963890

Inventors:

Wayne T. Babie - Poughkeepsie NY
Kenneth L. Devries - Hopewell Junction NY
Bang C. Nguyen - Wappingers Falls NY
Chau-Hwa J. Yang - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B44C 122
C03C 1500
C03C 2506

US Classification:

1566431

Abstract:

A two step method of etching a silicon nitride layer carrying a surface oxygen film from a substrate in a plasma reactor employs the steps of (1) a breakthrough step of employing a plasma of oxygen free etchant gases to break through and to remove the surface oxygen containing film from the surface of the silicon nitride layer, and (2) a main step of etching the newly exposed silicon nitride with etchant gases having high selectivity with respect to the silicon oxide underlying the silicon nitride. The plasma etching can be performed while employing magnetic- enhancement of the etching. The plasma etching is performed in a plasma reactor comprising a low pressure, single wafer tool. Plasma etching is performed while employing magnetic-enhancement of the etching. The etchant gases include a halide such as a bromide and a fluoride in the breakthrough step.

US Patent:

53288688, Jul 12, 1994

Filed:

Dec 10, 1992

Appl. No.:

7/989742

Inventors:

Richard A. Conti - Mount Kisco NY
Kenneth DeVries - Hopewell Junction NY
James F. White - Newburgh NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144
H01L 2148

US Classification:

437203

Abstract:

A metal connection for an integrated circuit device is effectively "cast" in place at any level of an integrated circuit. The "mold" for the connection is formed by depositing and patterning a sacrificial material, such as aluminum oxide or other metal oxides, and covering the sacrificial material with a protective material such as silicon dioxide or other insulators. After forming bore holes to the deposit of sacrificial material through the protective layer, the sacrificial material is removed by isotropic etching to form a cavity beneath and at least partially overlaid by the protective layer. Alternatively, a defect may be produced below the protective layer and filled with metal either with or without enlargement by further removal of material. This cavity is then filled with metal by deposition of the metal by, for instance, evaporation, sputtering and chemical vapor deposition or combinations thereof. Connections formed by this technique can be produced at any level of the integrated circuit and do not interfere with surface wiring.