Kenneth G Keels

US Patent:

6557115, Apr 29, 2003

Filed:

Nov 14, 2001

Appl. No.:

09/992193

Inventors:

Russel L. Gillenwater - Round Rock TX
Philip J. Brisky - Manchaca TX
Kenneth G. Keels - Austin TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

H02H 305

US Classification:

714 25, 714 18

Abstract:

The real-time test controller maintains a failure database containing a history of past failures for devices under test and selectively sorts the history for the device to be tested. The diagnostic testing sequence is then rearranged with tests having higher failure rates being conducted first. If faults are detected, a message is provided to the operator and the failure database is either manually or automatically updated with the latest fault information. In this manner, a continuously updated history of faults is maintained and the most efficient testing sequence is followed, resulting in significant time and cost savings.

US Patent:

7782905, Aug 24, 2010

Filed:

Feb 17, 2006

Appl. No.:

11/357449

Inventors:

Kenneth G. Keels - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
Vadim G. Makhervaks - Austin TX, US
Eric Jon Schneider - Cedar Park TX, US

Assignee:

Intel-NE, Inc. - Wilmington DE

International Classification:

H04J 3/24

US Classification:

370474, 714758, 714766

Abstract:

A mechanism for performing remote direct memory access (RDMA) operations between a first server and a second server. The apparatus includes a packet parser and a protocol engine. The packet parser processes a TCP segment within an arriving network frame, where the packet parser performs one or more speculative CRC checks according to an upper layer protocol (ULP), and where the one or more speculative CRC checks are performed concurrent with arrival of the network frame. The protocol engine is coupled to the packet parser. The protocol engine receives results of the one or more speculative CRC checks, and selectively employs the results for validation of a framed protocol data unit (FPDU) according to the ULP.

US Patent:

7849232, Dec 7, 2010

Filed:

Feb 17, 2006

Appl. No.:

11/356501

Inventors:

Robert O. Sharp - Round Rock TX, US
Kenneth G. Keels - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
John S. Lacombe - Austin TX, US

Assignee:

Intel-NE, Inc. - Wilmington DE

International Classification:

G06F 3/00
G06F 15/167
G06F 15/173
G06F 9/455

US Classification:

710 8, 709212, 709223, 709226, 718 1, 718100

Abstract:

A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.

US Patent:

7889762, Feb 15, 2011

Filed:

Jan 19, 2007

Appl. No.:

11/624849

Inventors:

Kenneth G. Keels - Georgetown TX, US
Jeff M. Carlson - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
David J. Maguire - Round Rock TX, US

Assignee:

Intel-NE, Inc. - Wilmington DE

International Classification:

H04J 3/24

US Classification:

370474, 370464, 709250, 714699, 714746, 714752, 714758

Abstract:

An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.

US Patent:

8032664, Oct 4, 2011

Filed:

Sep 2, 2010

Appl. No.:

12/874739

Inventors:

Robert O. Sharp - Round Rock TX, US
Kenneth G. Keels - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
John S. Lacombe - Austin TX, US

Assignee:

Intel-Ne, Inc. - Wilmington DE

International Classification:

G06F 3/00
G06F 15/167
G06F 15/173
G06F 9/455

US Classification:

710 8, 709212, 709223, 709226, 718 1, 718100

Abstract:

A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.

US Patent:

8078743, Dec 13, 2011

Filed:

Feb 17, 2006

Appl. No.:

11/356493

Inventors:

Robert O. Sharp - Round Rock TX, US
Kenneth G. Keels - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
Eric Rose - Cedar Park TX, US

Assignee:

Intel-NE, Inc. - Wilmington DE

International Classification:

G06F 15/16

US Classification:

709230, 709223, 709250, 709233, 370412, 370419

Abstract:

A computer system such as a server pipelines RNIC interface (RI) management/control operations such as memory registration operations to hide from network applications the latency in performing RDMA work requests caused in part by delays in processing the memory registration operations and the time required to execute the registration operations themselves. A separate QP-like structure, called a control QP (CQP), interfaces with a control processor (CP) to form a control path pipeline, separate from the transaction pipeline, which is designated to handle all control path traffic associated with the processing of RI control operations. This includes memory registration operations (MR OPs), as well as the creation and destruction of traditional QPs for processing RDMA transactions. Once the MR OP has been queued in the control path pipeline of the adapter, a pending bit is set which is associated with the MR OP. Processing of an RDMA work request in the transaction pipeline that has engendered the enqueued MR OP is permitted to proceed as if the processing of the MR OP has already been completed.

US Patent:

8271694, Sep 18, 2012

Filed:

Aug 26, 2011

Appl. No.:

13/219145

Inventors:

Robert O. Sharp - Round Rock TX, US
Kenneth G. Keels - Georgetown TX, US
Brian S. Hausauer - Austin TX, US
John S. Lacombe - Austin TX, US

Assignee:

Intel-Ne, Inc. - Wilmington DE

International Classification:

G06F 3/00
G06F 15/167
G06F 15/173
G06F 9/455

US Classification:

710 8, 709212, 709223, 709226, 718 1, 718100

Abstract:

A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.

US Patent:

8458280, Jun 4, 2013

Filed:

Dec 22, 2005

Appl. No.:

11/315685

Inventors:

Brian S. Hausauer - Austin TX, US
Tristan T. Gross - Austin TX, US
Kenneth G. Keels - Georgetown TX, US
Shaun V. Wandler - Austin TX, US

Assignee:

Intel-NE, Inc. - Santa Clara CA

International Classification:

G06F 15/167

US Classification:

709212, 709216

Abstract:

A mechanism for performing remote direct memory access (RDMA) operations between a first server and a second server over an Ethernet fabric. The RDMA operations are initiated by execution of a verb according to a remote direct memory access protocol. The verb is executed by a CPU on the first server. The apparatus includes transaction logic that is configured to process a work queue element corresponding to the verb, and that is configured to accomplish the RDMA operations over a TCP/IP interface between the first and second servers, where the work queue element resides within first host memory corresponding to the first server. The transaction logic includes transmit history information stores and a protocol engine. The transmit history information stores maintains parameters associated with said work queue element. The protocol engine is coupled to the transmit history information stores and is configured to access the parameters to enable retransmission of one or more TCP segments corresponding to the RDMA operations.