Kenneth R Mcelvain

US Patent:

6389586, May 14, 2002

Filed:

Dec 9, 1999

Appl. No.:

09/458545

Inventors:

Kenneth S. McElvain - Los Altos CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1710

US Classification:

716 18, 716 8, 716 12

Abstract:

A method comprising determining a state machine design point from a plurality of state machine design point options, where one of the plurality of state machine design point options corresponds to a safe design point. Then, forming a safe state machine model, if the safe design point is the determined state machine design point; where the safe state machine model has valid state logic separated from invalid state logic. Another method comprising detecting an invalid state of a state machine with invalid state logic. Then, setting a state machine register to a valid state with the invalid state logic. Then, continuing valid state operation of the state machine with valid state logic, where the valid state logic is separated from the invalid state logic.

US Patent:

6438735, Aug 20, 2002

Filed:

May 17, 1999

Appl. No.:

09/310882

Inventors:

Kenneth S. McElvain - Los Altos CA
Robert Erickson - Cupertino CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 7, 716 1

Abstract:

Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTL netlist is mapped to a particular target technology (e. g. a particular IC vendors architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e. g. field programmable gate arrays). In an example of another method, an HDL code is compiled to produce an RTL netlist representation which specifies a plurality of ICs in which logic, designed for placement on one of the plurality of ICs, is replicated for placement on another one of the plurality of ICs.

US Patent:

6449762, Sep 10, 2002

Filed:

Oct 7, 1999

Appl. No.:

09/414993

Inventors:

Kenneth S. McElvain - Los Altos CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 18

Abstract:

A method and apparatus that maintains the correspondence between a text representation of a circuit element and the corresponding schematic representation of the element after optimization of the circuit containing the element. In one example of a method of the invention, a circuit containing element is described in text representation. A first tag is assigned to the text representation. The text representation is synthesized to produce a first schematic representation of the circuit element. A second tag corresponding to the first tag is assigned to the first schematic representation of the circuit element. The circuit containing the circuit element is optimized to produce a second schematic representation of the circuit element. A third tag corresponding to the first tag is assigned to the second schematic representation. Other methods and apparatuses are described.

US Patent:

6519754, Feb 11, 2003

Filed:

May 17, 1999

Appl. No.:

09/313225

Inventors:

Kenneth S. McElvain - Los Altos CA
Robert Erickson - Cupertino CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 18, 716 2, 716 5

Abstract:

Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.

US Patent:

6618835, Sep 9, 2003

Filed:

Sep 7, 2001

Appl. No.:

09/949219

Inventors:

Krishna Garlapati - Santa Clara CA
Kenneth S. McElvain - Los Altos CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 3, 716 16, 716 4

Abstract:

One embodiment of the present invention identifies a circuit having a loop structure and a tri-state element. The circuit provides a circuit output. The loop structure contains at least a loop element in a feedback connection. The tri-state element receives first tri-state inputs. The circuit is transformed so that the tri-state element is moved across the loop structure to provide the circuit output.

US Patent:

6643829, Nov 4, 2003

Filed:

Dec 6, 2001

Appl. No.:

10/016214

Inventors:

Drazen Borkovic - Mountain View CA
Kenneth S. McElvain - Los Altos CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 3, 716 4

Abstract:

One embodiment of the present invention includes a technique for a gated clock conversion for a circuit which includes a gating circuit and a sequential element. The gating circuit has a gated clock net that drives a clock input of the sequential element. The sequential element receives a first input net at a data input and generates an output net. The gating circuit has a user-defined clock net. The technique includes determining the gating circuit and transforming the gating circuit to provide a second input net to the sequential element based on a cofactor condition of the gating circuit.

US Patent:

6668364, Dec 23, 2003

Filed:

Jun 3, 2002

Appl. No.:

10/162270

Inventors:

Kenneth S. McElvain - Los Altos CA
Robert Erickson - Cupertino CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 7, 716 5

Abstract:

Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTh netlist is mapped to a particular target technology (e. g. a particular IC vendors architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e. g. field programmable gate arrays). Other examples of methods and apparatuses are described.

US Patent:

6687882, Feb 3, 2004

Filed:

Jan 31, 2002

Appl. No.:

10/066093

Inventors:

Kenneth S. McElvain - Los Altos CA
Sanjeev Mahajan - San Francisco CA

Assignee:

Synplicity, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 3, 716 5, 716 7, 703 15

Abstract:

Methods and systems for designing integrated circuits. In one exemplary method, matched registers between the two netlists are determined. The matched registers become cut off points to generate primary inputs and outputs. When there are one or more unmatched registers between the first netlist and the second netlist, the unmatched registers are pushed to the primary inputs or outputs using retiming. At the primary inputs, a subspace generator is used to generate subspaces. The subspaces are used to identify non-equivalences between the first and second netlists. Other features and embodiments are also described.