Taro Contracting 2010 - 2012
Windows Application Designer and Programmer
Marvell Semiconductor 2010 - 2012
Principal Silicon Validation Engineer
Intel Corporation 1995 - 2002
Validation Engineer
Education:
Georgia Institute of Technology
Master of Science, Masters, Electrical Engineering
Missouri University of Science and Technology
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Embedded Systems Debugging Verilog Processors Arm Architecture Microprocessors System on A Chip Semiconductors Application Specific Integrated Circuits Testing C Dsi Csi Qt Pcie C++ Embedded Engineering Test Plan/Card Development Project Support Validation Engineering Systems Analysis System Design/Planning Validation Methodologies Root Cause/Failure Analysis Cross Functional Collaboration Strategic Planning C/C++ Process Improvement Team Coaching/Mentoring Application Engineers
PRIME TECHNOLOGIES INC West Chester, PA Jul 2011 to Jul 2012 Sales Account ManagerTHERMO FISHER SCIENTIFIC
Jan 2006 to Feb 2011 Account ManagerTHERMO FISHER SCIENTIFIC
Jan 2003 to Jan 2006 Site ManagerEXPRESS SCRIPTS, INC Bensalem, PA May 2002 to Jan 2003 Operations ManagerKULICKE AND SOFFA INDUSTRIES, INC Willow Grove, PA May 2000 to Feb 2002 Software Marketing ManagerKULICKE AND SOFFA INDUSTRIES, INC Willow Grove, PA Aug 1999 to May 2000 Used Equipment Production SupervisorKULICKE AND SOFFA INDUSTRIES, INC Chatsworth, CA Sep 1998 to Aug 1999 Process Engineer/ConsultantKULICKE AND SOFFA INDUSTRIES, INC Chandler, AZ Jan 1997 to Sep 1998 Account/Site Manager
Education:
University of Phoenix King of Prussia, PA 1997 to 2001 BS in Business AdministrationRETS Electronic School Broomall, PA 1984 to 1985 Micro-Electronics Technical in Electronics Engineering Technology
Military:
Rank: E-4 Sergeant Feb 1986 to Jan 1990 Branch: United States Air ForceL.i.location.original