Kenneth E Shoemaker

US Patent:

20190304953, Oct 3, 2019

Filed:

May 28, 2019

Appl. No.:

16/424355

Inventors:

- Santa Clara CA, US
Andre SCHAEFER - Sasssenburg, DE
Warren MORROW - Steilacoom WA, US
John B. HALBERT - Beaverton OR, US
Jin KIM - Portland OR, US
Kenneth D. SHOEMAKER - Los Altos Hills CA, US

International Classification:

H01L 25/065
H01L 23/48
G11C 5/06
H01L 27/108

Abstract:

A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

US Patent:

20180122779, May 3, 2018

Filed:

Sep 8, 2017

Appl. No.:

15/699750

Inventors:

- Santa Clara CA, US
Andre SCHAEFER - Sasssenburg, DE
Warren MORROW - Steilacoom WA, US
John B. HALBERT - Beaverton OR, US
Jin KIM - Portland OR, US
Kenneth D. SHOEMAKER - Los Altos Hills CA, US

International Classification:

H01L 25/065
H01L 27/108
H01L 23/48
G11C 5/06
H01L 23/00

Abstract:

A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

US Patent:

20150108660, Apr 23, 2015

Filed:

Dec 31, 2014

Appl. No.:

14/588183

Inventors:

- Santa Clara CA, US
Andre Schaefer - Braunschweig, DE
Warren Morrow - Steilacoom WA, US
John Halbert - Beaverton OR, US
Jin Kim - Beaverton OR, US
Kenneth Shoemaker - Los Altos Hills CA, US

International Classification:

H01L 25/065
G11C 5/06
H01L 27/108
H01L 23/48

US Classification:

257774

Abstract:

A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.