Kenneth Jay Shoemaker

US Patent:

6898694, May 24, 2005

Filed:

Jun 28, 2001

Appl. No.:

09/896346

Inventors:

Sailesh Kottapalli - Milpitas CA, US
James S. Burns - Cupertino CA, US
Kenneth D. Shoemaker - Los Altos Hills CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F009/48

US Classification:

712207, 711140, 711213, 712206, 712245

Abstract:

The present invention provides a mechanism for supporting high bandwidth instruction fetching in a multi-threaded processor. A multi-threaded processor includes an instruction cache (I-cache) and a temporary instruction cache (TIC). In response to an instruction pointer (IP) of a first thread hitting in the I-cache, a first block of instructions for the thread is provided to an instruction buffer and a second block of instructions for the thread are provided to the TIC. On a subsequent clock interval, the second block of instructions is provided to the instruction buffer, and first and second blocks of instructions from a second thread are loaded into a second instruction buffer and the TIC, respectively.

US Patent:

7685451, Mar 23, 2010

Filed:

Dec 20, 2002

Appl. No.:

10/327441

Inventors:

James S. Burns - Cupertino CA, US
Kenneth D. Shoemaker - Los Altos Hills CA, US
Sudarshan Kumar - Fremont CA, US
Tom E. Wang - Milpitas CA, US
David J. Ayers - Fremont CA, US
Vivek Tiwari - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713340, 713300, 327538

Abstract:

A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

US Patent:

20120249218, Oct 4, 2012

Filed:

Mar 31, 2011

Appl. No.:

13/077661

Inventors:

KENNETH D. SHOEMAKER - Los Altos Hills CA, US

International Classification:

H03K 5/00

US Classification:

327512

Abstract:

A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

US Patent:

20120249219, Oct 4, 2012

Filed:

Dec 23, 2011

Appl. No.:

13/336806

Inventors:

Kenneth D. Shoemaker - Los Altos Hills CA, US

International Classification:

H03K 5/00

US Classification:

327512

Abstract:

A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

US Patent:

20130292840, Nov 7, 2013

Filed:

Dec 2, 2011

Appl. No.:

13/997152

Inventors:

Kenneth Shoemaker - Los Altos Hills CA, US
Pete Vogt - Boulder CO, US

International Classification:

H01L 25/065

US Classification:

257773

Abstract:

A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

US Patent:

50739697, Dec 17, 1991

Filed:

Aug 1, 1988

Appl. No.:

7/227078

Inventors:

Kenneth D. Shoemaker - Saratoga CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 300

US Classification:

395725

Abstract:

A bus interface unit for a microprocessor which has an internal data bus of n bytes where n is greater than 2 for sensing and responding to enabling signals from external memory circuitry. The microprocessor provides address signals (31) for an n byte transfer (read or write) of data. Input pins receive at least one signal (byte size signal (34 or 35)) which indicates the number of bytes that the memory will transfer on the next ready signal. The microprocessor includes an output line for providing a last signal indicating that a data transfer request by the microprocessor will be satisfied with the data transfer occurring at the next ready signal. Logic circuit (44) is provided in the microprocessor for generating the last signal. This circuit (44) keeps track of the number of bytes that have been transferred, and it periodically senses the byte sizing signals (34 and 35). The logic circuit (44) is able to change the status of the last signal (29) "on the fly".

US Patent:

55862764, Dec 17, 1996

Filed:

Sep 6, 1994

Appl. No.:

8/301313

Inventors:

Edward Grochowski - San Jose CA
Kenneth Shoemaker - Saratoga CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 900

US Classification:

395380

Abstract:

Apparatus for determining the length of an instruction being processed by a computer system when instructions vary in length and appear sequentially in an instruction stream without differentiation between instructions including apparatus for providing an end bit for each predesignated length of an instruction to indicate that the instruction ends at that point in its length, apparatus for setting the end bit at the particular predesignated length of the instruction which is the actual end of the instruction, a first channel for processing a first instruction in sequence, a second channel for processing an instruction next following the first instruction, and apparatus for looking at the end bits of an instruction being processed by the first channel to determine the end point of that instruction and the beginning of the next instruction from the stream of instructions.

US Patent:

54506050, Sep 12, 1995

Filed:

Jan 28, 1993

Appl. No.:

8/010360

Inventors:

Edward Grochowski - San Jose CA
Kenneth Shoemaker - Los Altos Hills CA
Uri Weiser - Haifa, IL
Doron Orenstein - Haifa, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1204
G06F 1316

US Classification:

395800

Abstract:

The specification discloses a method and apparatus for determining the length of variable-length instructions that appear sequentially in an instruction stream without differentiation. The apparatus may be used to facilitate parallel processing of such variable-length instructions by a computer system. The apparatus includes: a circuit for providing a boundary marker for each instruction to indicate a boundary between that instruction and another instruction in the instruction stream, a circuit for processing instructions in sequence, a circuit for determining an actual boundary of a first instruction as it is processed, a circuit for comparing the boundary marker and the actual boundary of the first instruction to determine whether they match, a circuit for updating the boundary marker of the first instruction to the actual boundary of the first instruction when the boundary value and the actual boundary of the first instruction do not match, and a circuit for indicating a boundary between the first instruction and a next instruction from the stream of instructions based on the boundary marker of the first instruction.