Kenneth W Shoemaker

US Patent:

6898694, May 24, 2005

Filed:

Jun 28, 2001

Appl. No.:

09/896346

Inventors:

Sailesh Kottapalli - Milpitas CA, US
James S. Burns - Cupertino CA, US
Kenneth D. Shoemaker - Los Altos Hills CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F009/48

US Classification:

712207, 711140, 711213, 712206, 712245

Abstract:

The present invention provides a mechanism for supporting high bandwidth instruction fetching in a multi-threaded processor. A multi-threaded processor includes an instruction cache (I-cache) and a temporary instruction cache (TIC). In response to an instruction pointer (IP) of a first thread hitting in the I-cache, a first block of instructions for the thread is provided to an instruction buffer and a second block of instructions for the thread are provided to the TIC. On a subsequent clock interval, the second block of instructions is provided to the instruction buffer, and first and second blocks of instructions from a second thread are loaded into a second instruction buffer and the TIC, respectively.

US Patent:

7685451, Mar 23, 2010

Filed:

Dec 20, 2002

Appl. No.:

10/327441

Inventors:

James S. Burns - Cupertino CA, US
Kenneth D. Shoemaker - Los Altos Hills CA, US
Sudarshan Kumar - Fremont CA, US
Tom E. Wang - Milpitas CA, US
David J. Ayers - Fremont CA, US
Vivek Tiwari - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713340, 713300, 327538

Abstract:

A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

US Patent:

7877619, Jan 25, 2011

Filed:

Dec 31, 2007

Appl. No.:

11/967920

Inventors:

Ramana Rachakonda - Austin TX, US
Blaise Fanning - Folsom CA, US
Anil K Sabbavarapu - Austin TX, US
Belliappa M. Kuttanna - Austin TX, US
Rajesh Patel - Austin TX, US
Kenneth D. Shoemaker - Los Altos Hills CA, US
Lance E. Hacking - Austin TX, US
Bruce L. Fleming - Chandler AZ, US
Ashish V. Choubal - Austin TX, US

International Classification:

G06F 1/26
G06F 1/00

US Classification:

713310, 713330, 713340

Abstract:

In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states.

US Patent:

20120249218, Oct 4, 2012

Filed:

Mar 31, 2011

Appl. No.:

13/077661

Inventors:

KENNETH D. SHOEMAKER - Los Altos Hills CA, US

International Classification:

H03K 5/00

US Classification:

327512

Abstract:

A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

US Patent:

20120249219, Oct 4, 2012

Filed:

Dec 23, 2011

Appl. No.:

13/336806

Inventors:

Kenneth D. Shoemaker - Los Altos Hills CA, US

International Classification:

H03K 5/00

US Classification:

327512

Abstract:

A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

US Patent:

20130272049, Oct 17, 2013

Filed:

Dec 2, 2011

Appl. No.:

13/997148

Inventors:

Pete Vogt - Boulder CO, US
Andre Schaefer - Braunschweig, DE
Warren Morrow - Steilacoom WA, US
John Halbert - Beaverton OR, US
Jin Kim - Beaverton OR, US
Kenneth Shoemaker - Los Altos Hills CA, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

G11C 5/06
H01L 23/48

US Classification:

365 63, 257774

Abstract:

Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

US Patent:

20130292840, Nov 7, 2013

Filed:

Dec 2, 2011

Appl. No.:

13/997152

Inventors:

Kenneth Shoemaker - Los Altos Hills CA, US
Pete Vogt - Boulder CO, US

International Classification:

H01L 25/065

US Classification:

257773

Abstract:

A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

US Patent:

20140013070, Jan 9, 2014

Filed:

Dec 23, 2011

Appl. No.:

13/997977

Inventors:

Brian Toronyi - Austin TX, US
Kenneth Shoemaker - Los Altos Hills CA, US

International Classification:

G06F 12/00

US Classification:

711167

Abstract:

Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misaligment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.