Kenneth Shoemaker

US Patent:

7877619, Jan 25, 2011

Filed:

Dec 31, 2007

Appl. No.:

11/967920

Inventors:

Ramana Rachakonda - Austin TX, US
Blaise Fanning - Folsom CA, US
Anil K Sabbavarapu - Austin TX, US
Belliappa M. Kuttanna - Austin TX, US
Rajesh Patel - Austin TX, US
Kenneth D. Shoemaker - Los Altos Hills CA, US
Lance E. Hacking - Austin TX, US
Bruce L. Fleming - Chandler AZ, US
Ashish V. Choubal - Austin TX, US

International Classification:

G06F 1/26
G06F 1/00

US Classification:

713310, 713330, 713340

Abstract:

In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states.

US Patent:

20130272049, Oct 17, 2013

Filed:

Dec 2, 2011

Appl. No.:

13/997148

Inventors:

Pete Vogt - Boulder CO, US
Andre Schaefer - Braunschweig, DE
Warren Morrow - Steilacoom WA, US
John Halbert - Beaverton OR, US
Jin Kim - Beaverton OR, US
Kenneth Shoemaker - Los Altos Hills CA, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

G11C 5/06
H01L 23/48

US Classification:

365 63, 257774

Abstract:

Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

US Patent:

20140013070, Jan 9, 2014

Filed:

Dec 23, 2011

Appl. No.:

13/997977

Inventors:

Brian Toronyi - Austin TX, US
Kenneth Shoemaker - Los Altos Hills CA, US

International Classification:

G06F 12/00

US Classification:

711167

Abstract:

Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misaligment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.