Kenneth J Shoemaker

US Patent:

50739697, Dec 17, 1991

Filed:

Aug 1, 1988

Appl. No.:

7/227078

Inventors:

Kenneth D. Shoemaker - Saratoga CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 300

US Classification:

395725

Abstract:

A bus interface unit for a microprocessor which has an internal data bus of n bytes where n is greater than 2 for sensing and responding to enabling signals from external memory circuitry. The microprocessor provides address signals (31) for an n byte transfer (read or write) of data. Input pins receive at least one signal (byte size signal (34 or 35)) which indicates the number of bytes that the memory will transfer on the next ready signal. The microprocessor includes an output line for providing a last signal indicating that a data transfer request by the microprocessor will be satisfied with the data transfer occurring at the next ready signal. Logic circuit (44) is provided in the microprocessor for generating the last signal. This circuit (44) keeps track of the number of bytes that have been transferred, and it periodically senses the byte sizing signals (34 and 35). The logic circuit (44) is able to change the status of the last signal (29) "on the fly".

US Patent:

55862764, Dec 17, 1996

Filed:

Sep 6, 1994

Appl. No.:

8/301313

Inventors:

Edward Grochowski - San Jose CA
Kenneth Shoemaker - Saratoga CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 900

US Classification:

395380

Abstract:

Apparatus for determining the length of an instruction being processed by a computer system when instructions vary in length and appear sequentially in an instruction stream without differentiation between instructions including apparatus for providing an end bit for each predesignated length of an instruction to indicate that the instruction ends at that point in its length, apparatus for setting the end bit at the particular predesignated length of the instruction which is the actual end of the instruction, a first channel for processing a first instruction in sequence, a second channel for processing an instruction next following the first instruction, and apparatus for looking at the end bits of an instruction being processed by the first channel to determine the end point of that instruction and the beginning of the next instruction from the stream of instructions.

US Patent:

54506050, Sep 12, 1995

Filed:

Jan 28, 1993

Appl. No.:

8/010360

Inventors:

Edward Grochowski - San Jose CA
Kenneth Shoemaker - Los Altos Hills CA
Uri Weiser - Haifa, IL
Doron Orenstein - Haifa, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1204
G06F 1316

US Classification:

395800

Abstract:

The specification discloses a method and apparatus for determining the length of variable-length instructions that appear sequentially in an instruction stream without differentiation. The apparatus may be used to facilitate parallel processing of such variable-length instructions by a computer system. The apparatus includes: a circuit for providing a boundary marker for each instruction to indicate a boundary between that instruction and another instruction in the instruction stream, a circuit for processing instructions in sequence, a circuit for determining an actual boundary of a first instruction as it is processed, a circuit for comparing the boundary marker and the actual boundary of the first instruction to determine whether they match, a circuit for updating the boundary marker of the first instruction to the actual boundary of the first instruction when the boundary value and the actual boundary of the first instruction do not match, and a circuit for indicating a boundary between the first instruction and a next instruction from the stream of instructions based on the boundary marker of the first instruction.

US Patent:

51796791, Jan 12, 1993

Filed:

Jul 26, 1991

Appl. No.:

7/739772

Inventors:

Kenneth D. Shoemaker - Saratoga CA

International Classification:

G11C 700
G06F 1202

US Classification:

395425

Abstract:

A microprocessor is described which includes on a single substrate a central processing unit (CPU), write buffer and cache memory. The write buffer includes storage in each of its sections for a bit which indicates a hit/miss condition for the write cycle data stored in that section of the write buffer. If all these bits indicate that the new data in the write buffer has also been written into the cache memory, then read cycles are permitted before the data in the write buffer is written to external memory.

US Patent:

60556528, Apr 25, 2000

Filed:

May 19, 1999

Appl. No.:

9/314439

Inventors:

Nazar A. Zaidi - San Jose CA
Kenneth D. Shoemaker - Los Altos Hills CA
Gary N. Hammond - Campbell CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1116

US Classification:

714 53

Abstract:

A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possible address within the segment for each size of memory access. During a subsequent memory access, the limit corresponding to the segment being accessed and the length of memory access is selected. The selected limit is compared against the address of the memory access to determine if a limit violation has occurred. If a limit violation has occurred, a flag is set that, when read, will cause an exception.

US Patent:

54758246, Dec 12, 1995

Filed:

Feb 10, 1995

Appl. No.:

8/386595

Inventors:

Edward T. Grochowski - San Jose CA
Kenneth D. Shoemaker - Saratoga CA
Ahmad Zaidi - Santa Clara CA
Donald B. Alpert - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 928

US Classification:

395375

Abstract:

A computer system includes a dual instruction decoder which issues two instructions in parallel within a single clock cycle if their are no register dependencies between the instructions, and instructions fall within a predetermined subset of the complete instruction set. The system includes first and second instruction pipelines. The first pipeline executes any instruction issued from the full instruction set, while the second pipeline only executes a predetermined subset of instructions selected based on principles of locality. A register dependency checker determines whether the destination register of a first instruction is used during the execution of a second instruction in an instruction sequence. When both instructions are within the subset and there are no dependencies, the first and second instructions can be issued in parallel in the first and second pipelines.

US Patent:

60498978, Apr 11, 2000

Filed:

Jan 7, 1997

Appl. No.:

8/779791

Inventors:

Nazar A. Zaidi - San Jose CA
Kenneth D. Shoemaker - Los Altos Hills CA
Gary N. Hammond - Campbell CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1116

US Classification:

714 53

Abstract:

A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possible address within the segment for each size of memory access. During a subsequent memory access, the limit corresponding to the segment being accessed and the length of memory access is selected. The selected limit is compared against the address of the memory access to determine if a limit violation has occurred. If a limit violation has occurred, a flag is set that, when read, will cause an exception.