Kenneth P Snowdon

Address:

14 Slocum Dr, Falmouth, ME 04105

Phone:

2077978925

VIN:

2HGFA16567H500994

Make:

HONDA

Model:

CIVIC

Year:

2007

US Patent:

7068113, Jun 27, 2006

Filed:

Apr 1, 2004

Appl. No.:

10/814250

Inventors:

Hrvoje Jasa - Scarborough ME, US
Gary D. Polhemus - Sebago ME, US
Kenneth Patrick Snowdon - Falmouth ME, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G01R 23/00

US Classification:

331 44, 331 49

Abstract:

A direct calibration technique significantly tightens a tolerance band between multiple voltage controlled oscillators (VCOs), to correct for slight frequency mismatch between the multiple VCOs. The tightened tolerance band enhances the bit error rate (BER) and/or lengthens the possible consecutive identical digits (CIDs) length, and is particularly useful in integrated circuit applications. A Frequency Locked Loop (FLL), an accumulator, and a DAC are implemented to form a calibration loop that becomes far more digital in nature than a PLL, permitting greater embedded circuit test coverage and ease of integration in VLSI digital technologies. A frequency calibrated loop with digital accumulator and DAC in lieu of a PLL with associated charge pump integrator eliminates the need for large integrated capacitors, sensitivity to drift due to the leakage currents associated with deep sub-micron technologies, and embedded analog voltages which generally cannot be tested.

US Patent:

7477850, Jan 13, 2009

Filed:

Oct 31, 2005

Appl. No.:

11/263285

Inventors:

John E. Scoggins - Dover NH, US
James A. Siulinski - Westbrook ME, US
Kenneth P. Snowdon - Falmouth ME, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04B 10/04
H01S 3/00

US Classification:

398193, 398194, 372 3802, 372 3808

Abstract:

An optical transmission system comprises an electrical source and an electrical-to-optical converter. The electrical source is adapted to provide an electrical signal at an output thereof. The electrical-to-optical converter has an input coupled to the output of the electrical source and is operative to convert the electrical signal to a corresponding output optical signal. The electrical source comprises a pre-emphasis circuit or other electrical signal equalization circuitry configurable to control a waveform of the electrical signal so as to produce a desired level of jitter in the output optical signal.

US Patent:

7542533, Jun 2, 2009

Filed:

Jul 7, 2005

Appl. No.:

11/176444

Inventors:

Hrvoje Jasa - Scarborough ME, US
Gary D. Polhemus - Sebago ME, US
Kenneth P. Snowdon - Falmouth ME, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04L 7/00

US Classification:

375354, 375316, 375295, 375219, 327165, 327166, 327176, 37039562, 398155, 714 20

Abstract:

Embodiments of the invention include an apparatus and method for continuously calibrating the frequency of a clock and data recovery (CDR) circuit. The apparatus includes a delay arrangement that generates a gating signal, and a gated voltage-controlled oscillator that is enabled by the gating signal. The gated voltage-controlled oscillator generates a recovered clock signal that is based on the data signal input to the CDR circuit. The apparatus also includes a frequency control loop that continuously calibrates the gated voltage-controlled oscillator in such a way that the frequency of the clock signal generated by the gated voltage-controlled oscillator continues to be one half of the period of the data bits in the input data signal and the clock signal remains synchronized to the center of the data state transitions of the input data signal. Alternatively, a secondary frequency control loop adjusts the amount of delay in the frequency control loop.

US Patent:

7719324, May 18, 2010

Filed:

Apr 4, 2008

Appl. No.:

12/098230

Inventors:

Kenneth P. Snowdon - Falmouth ME, US
Ivan Duzevik - Portland ME, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03B 1/00

US Classification:

327108, 327 65, 327112, 326 82, 326 83

Abstract:

A low voltage differential signal (LVDS) transmitter with output power control. Internal sensing circuitry monitors output current flow through the termination impedance. When a proper termination impedance is not connected to the output, the resulting improper output current flow (e. g. , zero output current when no termination impedance is connected) is detected by the sensing circuitry, which causes the supply current to the output driver circuitry to be reduced. Additionally, further in response to such detection of improper output current flow, the sensing circuitry can cause the output voltage to be limited, e. g. , clamped, at a predetermined maximum magnitude.

US Patent:

8456225, Jun 4, 2013

Filed:

Dec 27, 2011

Appl. No.:

13/338198

Inventors:

Kenneth P. Snowdon - Falmouth ME, US

Assignee:

Fairchild Semiconductor Corporation - San Jose CA

International Classification:

G05F 1/10

US Classification:

327536, 363 60

Abstract:

Generally, this disclosure provides negative charge pump circuitry that is configured to supply a voltage that is less than a reference voltage (such as ground). The charge pump circuitry includes blocking circuitry that reduces or eliminates charge leakage so that a negative voltage may be developed at the output. The charge pump circuitry generally includes complimentary pairs of MOS switches that switch in a complimentary fashion according to charge developed on complimentary capacitors to provide a negative voltage power supply.

US Patent:

8525575, Sep 3, 2013

Filed:

Nov 12, 2010

Appl. No.:

12/945327

Inventors:

Kenneth P. Snowdon - Falmouth ME, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H03K 17/16

US Classification:

327391, 327388

Abstract:

A system includes a pass switch circuit and a first pass switch activation circuit. The pass switch circuit includes an impedance circuit and a pass transistor having a first source/drain connection, a second source/drain connection, and a gate input. The pass switch circuit passes an electronic signal from the first source/drain connection to the second source/drain connection in response to activation of the gate input. An impedance transfer function of the pass switch circuit is determined at least in part by an impedance of the impedance circuit and the impedance is sized to minimize attenuation of the electronic signal due to the impedance transfer function of the pass switch circuit. The first pass switch activation circuit provides a first activation signal to the gate input in response to an enable signal.

US Patent:

8542055, Sep 24, 2013

Filed:

Dec 23, 2010

Appl. No.:

12/977535

Inventors:

Kenneth P. Snowdon - Falmouth ME, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H03K 17/00

US Classification:

327403, 327404

Abstract:

A circuit for selectively providing a signal from a source to a sink is provided. The circuit includes a field effect transistor having a conducting state and a non-conducting state, the field effect transistor having a gate, a source, and a drain. The circuit also includes a first comparator configured to provide a first output based on a difference between a source voltage at the source of the field effect transistor and a first reference voltage. Finally, the circuit includes a switching amplifier configured to apply a first gate voltage to the gate of the field effect transistor as a function of the first output of the first comparator.

US Patent:

8564918, Oct 22, 2013

Filed:

Feb 16, 2011

Appl. No.:

13/028731

Inventors:

Nickole Gagne - Saco ME, US
Kenneth P. Snowdon - Falmouth ME, US

Assignee:

Fairchild Semiconductor Corporation - San Jose CA

International Classification:

H02H 3/00

US Classification:

361 86, 361 911

Abstract:

This document discusses methods and apparatus for preventing or reducing sub-threshold pass gate leakage. In an example, an apparatus can include a pass gate configured to electrically couple a first node with a second node in a first state and to electrically isolate the first node from the second node in a second state, control logic configured to control the pass gate, wherein the control logic includes a supply rail, and an over-voltage circuit configured to compare voltages received at a plurality of input nodes and to couple an output to an input node a highest voltage. In an example, the output of over-voltage circuit can be selectively coupled to the supply rail.