Kent L Anderson

Address:

11440 W 38 Ave, Wheat Ridge, CO 80033

VIN:

1D8GU28K67W643515

Make:

DODGE

Model:

NITRO

Year:

2007

US Patent:

6959412, Oct 25, 2005

Filed:

Jun 27, 2002

Appl. No.:

10/184758

Inventors:

Gregory Lee Silvus - Boulder CO, US
Kent Douglas Anderson - Broomfield CO, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

H03M013/31
H03M013/05

US Classification:

714778, 341 83, 714752, 714769

Abstract:

A method of encoding data includes representing the data as number(s) in a first base. The method further includes converting the number(s) into a number(s) in a second base. The resultant number in the second base can be viewed as data suitable for encoding using an ECC algorithm. After being ECC encoded, the data may be further modulation encoded. Modulation encoding may include transforming each symbol to a value that constrains run lengths of a binary value (e. g. , zero). A decoding method and system checks a received data block for erroneous symbols, maps each received, encoded symbol to an associated ECC-encoded transform pair. The ECC encoded data may be decoded and corrected using the ECC and the locations of identified erroneous symbols. Finally, the corrected data sequence is converted from the second base back to the first base, from which the original data is retrieved.

US Patent:

7196644, Mar 27, 2007

Filed:

Jul 1, 2004

Appl. No.:

10/883633

Inventors:

Kent D. Anderson - Broomfield CO, US
Gregory L. Silvus - Boulder CO, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

H03M 1/06

US Classification:

341118, 341155

Abstract:

A signal processing system includes a receiver for receiving an analog signal. The system also includes an analog-to-digital converter (ADC) coupled to the receiver. At each of a series of time intervals, the ADC outputs sequential digital codes. Each digital code corresponds to a sampled analog value of the received analog signal at each sample interval. The system further includes a memory in which the sequential digital codes may be stored, and a processing circuit for converting the digital codes into a series of binary data bits. The conversion may be performed in a different sequence than the sequence in which the digital codes are stored in the memory.

US Patent:

7365671, Apr 29, 2008

Filed:

Oct 10, 2006

Appl. No.:

11/545654

Inventors:

Kent D. Anderson - Broomfield CO, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

H03M 1/12

US Classification:

341155, 360 46, 360 51

Abstract:

Method and apparatus for processing transmitted data. A sampling circuit preferably performs lossy sampling of a continuous signal to provide a corresponding sequence of discrete samples at a sampling rate less than a Nyquist rate of the continuous signal. A processing circuit reconstructs an informational content of the continuous signal from the discrete samples, and operates to periodically insert additional samples into the sequence, which preferably increases an effective rate of said sampling to match or exceed the Nyquist rate. Preferably, the lossy discrete samples are temporarily stored in a memory space prior to reconstruction by the processing circuit. The sampling circuit preferably comprises an analog-to-digital converter (ADC) of an analog front end (AFE). The processing circuit preferably comprises a digital back end (DBE) employing partial-response, maximum-likelihood (PRML) detection. The additional samples are preferably provided by an iterative timing recovery (ITR) block of the DBE.

US Patent:

7379452, May 27, 2008

Filed:

Dec 21, 2001

Appl. No.:

10/028871

Inventors:

Richard T. Behrens - Louisville CO, US
Kent D. Anderson - Westminster CO, US
Alan J. Armstrong - Longmont CO, US
Trent Dudley - Littleton CO, US
Bill R. Foland - Littleton CO, US
Neal Glover - Broomfield CO, US
Larry D. King - Boulder CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 12/50

US Classification:

370359, 360 40, 360 51

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating analog as well as digital functions of the read channel in a single integrated circuit, and embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

7885255, Feb 8, 2011

Filed:

May 23, 2008

Appl. No.:

12/126188

Inventors:

Richard T. Behrens - Louisville CO, US
Kent D. Anderson - Westminster CO, US
Alan J. Armstrong - Longmont CO, US
Trent Dudley - Littleton CO, US
Bill R. Foland - Littleton CO, US
Neal Glover - Broomfield CO, US
Larry D. King - Boulder CO, US

Assignee:

Lake Cherokee Hard Drive Technologies, LLC - Longview TX

International Classification:

H04L 12/50

US Classification:

370359, 360 40, 360 51

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

7957370, Jun 7, 2011

Filed:

May 23, 2008

Appl. No.:

12/126188

Inventors:

Richard T. Behrens - Louisville CO, US
Kent D. Anderson - Westminster CO, US
Alan J. Armstrong - Longmont CO, US
Trent Dudley - Littleton CO, US
Bill R. Foland - Littleton CO, US
Neal Glover - Broomfield CO, US
Larry D. King - Boulder CO, US

Assignee:

Lake Cherokee Hard Drive Technologies, LLC - Longview TX

International Classification:

H04L 12/50

US Classification:

370359, 360 40, 360 51

Abstract:

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

US Patent:

8000053, Aug 16, 2011

Filed:

Dec 23, 2008

Appl. No.:

12/343285

Inventors:

Kent D. Anderson - Broomfield CO, US

Assignee:

Western Digital Technologies, Inc. - Irvine CA

International Classification:

G11B 5/455

US Classification:

360 75

Abstract:

A disk drive for determining a write jog value is disclosed. The disk drive comprises: a disk; a head including a reader and a writer; and a processor. The processor controls operations in the disk drive including: commanding the reader to track follow on a first track, wherein the writer is located over an uncalibrated track position; commanding the writer to write a first test pattern on a section of the disk; commanding the writer to move by a plurality of step amounts to write a plurality of test patterns; commanding the reader to move by a second plurality of step amounts to read the plurality of test patterns; determining a reader signal value associated with each test pattern; determining the uncalibrated track position based on the read signal values; and determining the write jog value based on the distance between the first track and the uncalibrated track position.

US Patent:

8593753, Nov 26, 2013

Filed:

Apr 22, 2010

Appl. No.:

12/765800

Inventors:

Kent D. Anderson - Broomfield CO, US

Assignee:

Western Digital Technologies, Inc. - Irvine CA

International Classification:

G11B 5/60
G11B 21/21

US Classification:

360 75

Abstract:

Systems and methods for detecting touchdown of a head on a disk are provided. In one embodiment, a disk drive comprises a thermal sensor configured to sense a temperature of a head and to generate a thermal signal based on the sensed temperature. The disk drive also comprises touchdown circuit configured to receive the thermal signal, to increment a count value each time the thermal signal exceeds a thermal threshold, and to output a fault signal when the count value is equal to or exceeds a count threshold.