Kenton T Dalton

US Patent:

6496962, Dec 17, 2002

Filed:

Nov 17, 2000

Appl. No.:

09/715814

Inventors:

Kenton Dalton - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 6, 716 18, 703 14

Abstract:

A method of generating a cell function and timing model library in a standard library format includes the steps of (a) receiving as input a model source file, a technology dependent file, and a cell list data file; (b) parsing a functional description for each cell in the cell list data file from the model source file; (c) expanding parameterized timing data for each cell in the cell list data file from the technology dependent file; and (d) generating as output a cell model library in a standard library format from the parameterized timing data.

US Patent:

6951017, Sep 27, 2005

Filed:

Jul 27, 2001

Appl. No.:

09/916958

Inventors:

Kenton T. Dalton - Fort Collins CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F009/44

US Classification:

717170, 717115, 703 4, 716 11

Abstract:

A software tool is created to migrate computer files that define ICs from older to newer computer-readable directory structures. The old and new directories are compared to identify differences that are mapped and sorted on the basis of directory source names. A computer file defining an IC is migrated by identifying source names in the file that are referenced by the tool. For each identified source name, the associated directory reference is changed from the old to the new directory structure.

US Patent:

7065734, Jun 20, 2006

Filed:

Jun 2, 2004

Appl. No.:

10/859857

Inventors:

Kenton T. Dalton - Fort Collins CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 18, 716 16, 716 17

Abstract:

A method and computer program are disclosed for generating a hardware description language configuration from a generic phase locked loop architecture that include steps of: (a) receiving as input values for a set of configuration variables for a phase locked loop; (b) applying the values for the set of configuration variables to a generic top level model of the phase locked loop to generate a specific configuration of the phase locked loop from the generic top level model; and (c) generating as output a hardware description language code for the specific configuration of the phase locked loop.

US Patent:

6453451, Sep 17, 2002

Filed:

Jun 12, 2001

Appl. No.:

09/880607

Inventors:

Viswanathan Lakshmanan - Westminster CO
Kenton Dalton - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 6, 716 17, 716 18

Abstract:

A method of generating a back-annotated standard delay format file for designing integrated circuits with conditional/moded delays is disclosed that includes the steps of receiving as inputs a main input file, a conditional delay specifications file, and a selected option switch; inserting delay information from the conditional delay specifications file for each cell entry in the main input file according to the selected option switch into an output data structure; and generating the back-annotated standard delay format file from the output data structure.