Kevin M Atkinson

US Patent:

6816562, Nov 9, 2004

Filed:

Jan 7, 2003

Appl. No.:

10/337494

Inventors:

Kevin E. Atkinson - Eden Prairie MN
Timothy H. Dwyer - Minneapolis MN
Ryan C. Johnson - Waconia MN
Mark D. Elpers - Elk River MN
Dirk R. Helgemo - Shakopee MN

Assignee:

MathStar, Inc. - Minneapolis MN

International Classification:

H03K 19177

US Classification:

376 39, 376 41, 376 47

Abstract:

A logic array is provided, which includes a plurality of unidirectional segmented buses connecting a plurality of processing elements, called silicon objects, within an integrated circuit. The bus includes a string of unidirectional bus segments. Each silicon object includes a bus input coupled to one of the bus segments in the first bus, and a bus output coupled to a next subsequent one of the bus segments in the first bus. A landing circuit is coupled to the bus input for receiving digital information from the bus input. A function-specific logic block is coupled to an output of the landing circuit and has a result output. Each silicon object further includes a multiplexer having first and second inputs coupled to the bus input and the result output, respectively, and having an output coupled to the bus output.

US Patent:

8097526, Jan 17, 2012

Filed:

Nov 4, 2009

Appl. No.:

12/612256

Inventors:

Kevin Atkinson - Chanhassen MN, US
Clifford H. Boler - Eden Prairie MN, US

Assignee:

CrossFire Technologies, Inc. - Eden Prairie MN

International Classification:

H01L 21/00

US Classification:

438464, 438458, 438459, 438626, 438631, 438645, 257692

Abstract:

Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.

US Patent:

8569879, Oct 29, 2013

Filed:

Jan 16, 2012

Appl. No.:

13/351142

Inventors:

Kevin Atkinson - Chanhassen MN, US
Clifford H. Boler - Eden Prairie MN, US

Assignee:

CrossFire Technologies, Inc. - Eden Prairie MN

International Classification:

H01L 23/52
H01L 29/40

US Classification:

257692, 257774, 257777

Abstract:

Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and (programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.

US Patent:

20160246675, Aug 25, 2016

Filed:

Feb 19, 2016

Appl. No.:

15/048701

Inventors:

- Austin TX, US
KEVIN E. ATKINSON - Chanhassen MN, US
JAMES A. JENSEN - Eagan MN, US

International Classification:

G06F 11/10
G11C 29/52

Abstract:

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.

US Patent:

20140281810, Sep 18, 2014

Filed:

Mar 15, 2014

Appl. No.:

14/214800

Inventors:

- Austin TX, US
KEVIN E. ATKINSON - Chanhassen MN, US
JAMES A. JENSEN - Eagan MN, US

International Classification:

G06F 11/10

US Classification:

714764

Abstract:

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.