Kevin N Duncan

US Patent:

6865660, Mar 8, 2005

Filed:

Jun 28, 2002

Appl. No.:

10/183370

Inventors:

Kevin Duncan - Roseville MN, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F012/00

US Classification:

711217, 711220, 365201, 708250, 714728, 714730, 714738, 714743

Abstract:

A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.

US Patent:

7072923, Jul 4, 2006

Filed:

Feb 15, 2005

Appl. No.:

11/057596

Inventors:

Kevin Duncan - Roseville MN, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 12/00

US Classification:

708250, 365201, 36523009, 711217, 714728, 714739

Abstract:

A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.

US Patent:

20210133358, May 6, 2021

Filed:

Jan 15, 2021

Appl. No.:

17/149870

Inventors:

- Boise ID, US
Kevin R. Duncan - Ramsey MN, US

International Classification:

G06F 21/62
G06F 9/30
G06F 9/4401
G06F 13/42

Abstract:

An example apparatus can include a memory device and a controller coupled to the memory device configured to receive a command including command information to access a register from a host device. The controller can grant access to the register in response to the controller determining the command is valid and/or deny access to the register in response to the controller determining the command is invalid. The controller can determine the command is valid by calculating an answer using a seed from the command in a formula and verifying the calculated answer matches an answer from the command. The command, once verified as valid, can allow the host device to access configuration registers and/or data registers.

US Patent:

20200379935, Dec 3, 2020

Filed:

Aug 18, 2020

Appl. No.:

16/996553

Inventors:

- Boise ID, US
Kevin R. Duncan - Ramsey MN, US

International Classification:

G06F 13/40
G06F 9/455
G06F 13/42
G06F 13/24

Abstract:

A peripheral component interconnect express (PCIe) physical function is coupled to a controller. The controller is configured to allocate a first portion of resources for use by the PCIe physical function. A PCIe virtual function is coupled to the controller. The is configured to allocate a second portion of resources for use by the PCIe virtual function based, at least in part, on a total number of PCIe physical functions and a total number of PCIe virtual functions associated with the apparatus.

US Patent:

20200293334, Sep 17, 2020

Filed:

May 28, 2020

Appl. No.:

16/885600

Inventors:

- Boise ID, US
Kevin R. Duncan - Ramsey MN, US

International Classification:

G06F 9/4401
G06F 12/02

Abstract:

An example apparatus can include a host device and an apparatus including a memory device and a controller coupled to the memory device, wherein the host device is configured to send a command to read an image to configure the host to boot from the memory device to the controller and wherein a base address register is configured to receive the command, indicate the size of the image, and redirect the command to a first image in memory using a first register that indicates a size of the first image and a second register that indicates a location of the first image.

US Patent:

20200089640, Mar 19, 2020

Filed:

Nov 25, 2019

Appl. No.:

16/693792

Inventors:

- Boise ID, US
Kevin R. Duncan - Ramsey MN, US

International Classification:

G06F 13/40
G06F 9/455
G06F 13/42
G06F 13/24

Abstract:

A peripheral component interconnect express (PCIe) physical function is coupled to a controller. The controller is configured to allocate a first portion of resources for use by the PCIe physical function. A PCIe virtual function is coupled to the controller. The is configured to allocate a second portion of resources for use by the PCIe virtual function based, at least in part, on a total number of PCIe physical functions and a total number of PCIe virtual functions associated with the apparatus.

US Patent:

20200042187, Feb 6, 2020

Filed:

Oct 14, 2019

Appl. No.:

16/600784

Inventors:

- Boise ID, US
Kevin R. Duncan - Ramsey MN, US

International Classification:

G06F 3/06
G06F 13/28
G06F 13/16

Abstract:

A command to duplicate data on a storage system is received from a host system, and in response to receiving the command, data corresponding to the command is retrieved from host memory of the host system. A plurality of write operations are performed on one or more memory devices of the storage system to fulfill the command, wherein performing each one of the plurality of write operations comprises writing the data to the one or more memory devices of the storage system without a subsequent retrieval of the data from the host memory.

US Patent:

20200042327, Feb 6, 2020

Filed:

Aug 2, 2018

Appl. No.:

16/052995

Inventors:

- Boise ID, US
Kevin R. Duncan - Ramsey MN, US

International Classification:

G06F 9/4401
G06F 12/02

Abstract:

An example apparatus can include a host device and an apparatus including a memory device and a controller coupled to the memory device, wherein the host device is configured to send a command to read an image to configure the host to boot from the memory device to the controller and wherein a base address register is configured to receive the command, indicate the size of the image, and redirect the command to a first image in memory using a first register that indicates a size of the first image and a second register that indicates a location of the first image.