Kevin G Kramer

US Patent:

6987761, Jan 17, 2006

Filed:

Feb 13, 2002

Appl. No.:

09/683777

Inventors:

Robert M. Bunce - Hopewell Junction NY, US
Louis T. Fasano - Poughkeepsie NY, US
Christos J. Georgiou - Scarsdale NY, US
Kevin G. Kramer - Wappingers Falls NY, US
Brian J. Schuh - Apex NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370389, 370391, 370394, 370428

Abstract:

A data communication controller processes incoming data frames. The controller includes a pre-processing block for receiving data frames and a frame processing unit coupled to the pre-processing block. The pre-processing block is configured to compare header fields of a current frame with header fields of a previous frame. The pre-processing block provides an output signal to the frame processing unit on the basis of the comparison of the header fields of the current and previous frames. The controller may operate in accordance with the Fiber Channel protocol, and the output signal may include bits to indicate that the current frame is of the same exchange, of the same sequence, and is next in sequence relative to the previous frame.

US Patent:

7278083, Oct 2, 2007

Filed:

Jun 27, 2003

Appl. No.:

10/604141

Inventors:

Jonathan M. Haswell - San Jose CA, US
Kevin G. Kramer - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 13/00

US Classification:

714758, 714763

Abstract:

A method of detecting error during transfer of instructions from a data memory to a computer processor. At the time of the commencement of transmission of the instructions, the raw data signal is checked for an error detection code indicating data corruption. If the error detection code indicates no data corruption, the transmission of the instruction to the computer processor is completed. However, if data corruption is indicated, the raw data signal is substituted with a predetermined reserved signal or instruction and transmitted to the computer processor. An attempt is made to correct the corrupted data in the raw data signal and, if it is corrected, the corrected data signal is subsequently retrieved and the corrected data signal is processed by the computer processor. The corrupted raw data signal in the data memory may be replaced with the corrected data signal.

US Patent:

7603609, Oct 13, 2009

Filed:

May 24, 2007

Appl. No.:

11/753127

Inventors:

Jonathan M Haswell - San Jose CA, US
Kevin G Kramer - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 13/00

US Classification:

714758, 714763

Abstract:

A method of detecting error during transfer of instructions from a data memory to a computer processor. At the time of the commencement of transmission of the instructions, the raw data signal is checked for an error detection code indicating data corruption. If the error detection code indicates no data corruption, the transmission of the instruction to the computer processor is completed. However, if data corruption is indicated, the raw data signal is substituted with a predetermined reserved signal or instruction and transmitted to the computer processor. An attempt is made to correct the corrupted data in the raw data signal and, if it is corrected, the corrected data signal is subsequently retrieved and the corrected data signal is processed by the computer processor. The corrupted raw data signal in the data memory may be replaced with the corrected data signal.

US Patent:

7675966, Mar 9, 2010

Filed:

Sep 29, 2006

Appl. No.:

11/537053

Inventors:

Robert M. Bunce - Hopewell Junction NY, US
William R. Kelly - Verbank NY, US
Kevin G. Kramer - Wappingers Falls NY, US
Dinesh B. Nair - Cochin IN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B 3/46

US Classification:

375224

Abstract:

A method for on-chip detection of data lock and measurement of data lock time in a high-speed serial data link, including: permitting one or more incoming data streams into the high-speed data link; establishing a pattern to be searched in the one or more incoming data streams; comparing patterns in the one or more incoming data streams to a programmable data pattern; holding a repetitive pattern of bits in the one or more incoming data streams by one or more programmable data pattern registers, wherein when one or more occurrences of a byte are detected, an appropriate bit in the one or more programmable data pattern registers is set to indicate the byte's relative position; and filtering false indications in the repetitive pattern by using a byte detection state machine, the state machine controlling and keeping track of a search progress.

US Patent:

7855563, Dec 21, 2010

Filed:

Jun 21, 2007

Appl. No.:

11/766268

Inventors:

Huihao Xu - Brooklyn NY, US
Louis L. Hsu - Fishkill NY, US
Kevin G. Kramer - Wappingers Falls NY, US
James D. Rockrohr - Hopewell Junction NY, US
Michael A. Sorna - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/00
H04B 3/46

US Classification:

324543, 324500, 375224

Abstract:

A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.

US Patent:

7873922, Jan 18, 2011

Filed:

Nov 19, 2007

Appl. No.:

11/985956

Inventors:

Huihao Xu - Brooklyn NY, US
Louis L. Hsu - Fishkill NY, US
Kevin G. Kramer - Wappingers Falls NY, US
James D. Rockrohr - Hopewell Junction NY, US
Michael A. Sorna - Hopwell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 1

Abstract:

A design structure embodied in a machine-readable medium used in a design process may include a system for detecting a fault in a signal transmission path. Such system may include, for example, a hysteresis comparator including a latch having n-type field effect transistor (“NFET”) storage elements. The hysteresis comparator may be operable to detect a crossing of a reference voltage level by an input signal arriving from the signal transmission path such that when the comparator does not detect an expected crossing of the reference voltage level by the input signal, the fault is determined to be detected in the signal transmission path.

US Patent:

20020124102, Sep 5, 2002

Filed:

Mar 1, 2001

Appl. No.:

09/797499

Inventors:

kevin Kramer - Wappingers Falls NY, US
Henry Tsou - San Jose CA, US
Chan Ng - San Jose CA, US
Christopher Taylor - Rochester MN, US
Kwan Yap - San Jose CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F015/16

US Classification:

709/234000

Abstract:

A device for controlling the flow of command messages in a network in order to alleviate full queue situations that may result in an overrun of commands. The device comprises a counter circuit for determining the number of buffers available in the command queue and a control circuit for controlling the flow of command frames. The control circuit includes a first and second means for storing and is responsive to a status of the command queue and control logic.

US Patent:

51736195, Dec 22, 1992

Filed:

Aug 5, 1991

Appl. No.:

7/740757

Inventors:

Gene J. Gaudenzi - Purdys NY
Kevin G. Kramer - Wappingers Falls NY
Susan L. Tempest - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19177

US Classification:

3072722

Abstract:

A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirection bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.