Kevin P Kramer

US Patent:

7855563, Dec 21, 2010

Filed:

Jun 21, 2007

Appl. No.:

11/766268

Inventors:

Huihao Xu - Brooklyn NY, US
Louis L. Hsu - Fishkill NY, US
Kevin G. Kramer - Wappingers Falls NY, US
James D. Rockrohr - Hopewell Junction NY, US
Michael A. Sorna - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/00
H04B 3/46

US Classification:

324543, 324500, 375224

Abstract:

A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.

US Patent:

7873922, Jan 18, 2011

Filed:

Nov 19, 2007

Appl. No.:

11/985956

Inventors:

Huihao Xu - Brooklyn NY, US
Louis L. Hsu - Fishkill NY, US
Kevin G. Kramer - Wappingers Falls NY, US
James D. Rockrohr - Hopewell Junction NY, US
Michael A. Sorna - Hopwell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 1

Abstract:

A design structure embodied in a machine-readable medium used in a design process may include a system for detecting a fault in a signal transmission path. Such system may include, for example, a hysteresis comparator including a latch having n-type field effect transistor (“NFET”) storage elements. The hysteresis comparator may be operable to detect a crossing of a reference voltage level by an input signal arriving from the signal transmission path such that when the comparator does not detect an expected crossing of the reference voltage level by the input signal, the fault is determined to be detected in the signal transmission path.

US Patent:

53134753, May 17, 1994

Filed:

Oct 31, 1991

Appl. No.:

7/785558

Inventors:

Daryl C. Cromer - Boca Raton FL
Gene J. Gaudenzi - Purdys NY
Paul C. King - Boca Raton FL
Kevin G. Kramer - Wappingers Falls NY
Timothy J. Louie - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 1300

US Classification:

371 401

Abstract:

An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.

US Patent:

51075075, Apr 21, 1992

Filed:

May 26, 1988

Appl. No.:

7/198961

Inventors:

Patrick M. Bland - Delray Beach FL
Mark E. Dean - Delray Beach FL
Gene J. Gaudenzi - Purdys NY
Kevin G. Kramer - Wappingers Falls NY
Susan L. Tempest - Poughkeepsie NY

Assignee:

International Business Machines - Armonk NY

International Classification:

G06F 1110

US Classification:

371 491

Abstract:

A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.