Kevin N Lin

US Patent:

8352646, Jan 8, 2013

Filed:

Dec 16, 2010

Appl. No.:

12/969651

Inventors:

Jason A. Cox - Raleigh NC, US
Omer Heymann - Tzofit, IL
Nadav Levison - Herut, IL
Kevin C. Lin - Raleigh NC, US
Eric F. Robinson - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28

US Classification:

710 23, 711118, 711135, 711141

Abstract:

Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.

US Patent:

8633551, Jan 21, 2014

Filed:

Jun 29, 2012

Appl. No.:

13/537573

Inventors:

Weng Hong Teh - Phoenix AZ, US
Kevin L. Lin - Beaverton OR, US
Feras Eid - Chandler AZ, US
Qing Ma - Saratoga CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/14

US Classification:

257414, 257686, 257E25001

Abstract:

A semiconductor package having a mechanical fuse therein and methods to form a semiconductor package having a mechanical fuse therein are described. For example, a semiconductor structure includes a semiconductor package. A semiconductor die is housed in the semiconductor package. A microelectromechanical system (MEMS) device is housed in the semiconductor package. The MEMS device has a suspended portion. A mechanical fuse is housed in the semiconductor package and either coupled to, or decoupled from, the suspended portion of the MEMS device.

US Patent:

20080288752, Nov 20, 2008

Filed:

May 4, 2008

Appl. No.:

12/114785

Inventors:

JASON A. COX - Raleigh NC, US
Kevin C.K. Lin - Raleigh NC, US
Eric F. Robinson - Raleigh NC, US

International Classification:

G06F 9/30

US Classification:

712208, 712E09028

Abstract:

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding store data to loads in a pipelined processor is provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operable to respectively execute a decoded instruction from the decoder. The plurality of execution units include a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations. The store queue is operable to buffer one or more store memory operations prior to the one or more memory operations being completed, and the store queue is operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis.

US Patent:

20120151142, Jun 14, 2012

Filed:

Dec 14, 2010

Appl. No.:

12/967086

Inventors:

Jason A. Cox - Raleigh NC, US
Kevin CK Lin - Raleigh NC, US
Eric F. Robinson - Raleigh NC, US
Mark J. Wolski - Apex NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 13/36
G06F 12/08

US Classification:

711118, 710107, 711E12017

Abstract:

An L2 cache, method and computer program product for transferring an inbound bus operation to a processor side handling machine. The method includes a bus operation handling machine accepting the inbound bus operation received over a system interconnect, the bus operation handling machine identifying a demand operation of the processor side handling machine that will complete the bus operation, the bus operation handling machine sending the identified demand operation to the processor side handling machine, and the processor side handling machine performing the identified demand operation.

US Patent:

20120159640, Jun 21, 2012

Filed:

Dec 16, 2010

Appl. No.:

12/969634

Inventors:

Jason A. Cox - Raleigh NC, US
Kevin C. Lin - Raleigh NC, US
Eric F. Robinson - Raleigh NC, US
Mark J. Wolski - Apex NC, US

Assignee:

Internationl Business Machines Corporation - Armonk NY

International Classification:

G06F 21/24

US Classification:

726 27

Abstract:

Acquiring access to a token controlled system resource, including: receiving, by a token broker, a command that requires access to the token controlled system resource, where the token broker is automated computing machinery for acquiring tokens and distributing the command to the token controlled system resource for execution; identifying, by the token broker, a first need state, the first need state indicating that the token broker requires access to the token controlled system resource to which the token broker does not possess a token; requesting, by the token broker, a configurable number of tokens to gain access to the token controlled system resource, without dispatching an operation handler for executing the command until at least one token is acquired; assigning, by the token broker, an acquired token to the operation handler; and dispatching, by the token broker, the operation handler and its assigned token for executing the command.

US Patent:

20120198178, Aug 2, 2012

Filed:

Jan 31, 2011

Appl. No.:

13/017250

Inventors:

Jason A. Cox - Raleigh NC, US
Robert J. Dorsey - Durham NC, US
Kevin CK Lin - Raleigh NC, US
Eric F. Robinson - Raleigh NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/08

US Classification:

711145, 711E12032

Abstract:

One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.

US Patent:

20190103345, Apr 4, 2019

Filed:

Sep 29, 2017

Appl. No.:

15/721707

Inventors:

- Santa Clara CA, US
Venkata Suresh R. GUTHIKONDA - Chandler AZ, US
Patrick NARDI - Scottsdale AZ, US
Santosh SANKARASUBRAMANIAN - Chandler AZ, US
Kevin Y. LIN - Chandler AZ, US
Leigh M. TRIBOLET - Chandler AZ, US
John L. HARPER - Chandler AZ, US
Pramod MALATKAR - Chandler AZ, US

International Classification:

H01L 23/498
H01L 23/367
H01L 21/50
H01L 23/52
H01L 23/00
H05K 1/02

Abstract:

An apparatus, comprising a first platform comprising a first working surface having a first non-planar portion; and a second platform comprising a second working surface having a second non-planar portion, wherein: the second working surface is opposite the first working surface, a distance between the first working surface and the second working surface is adjustable, the first non-planar portion comprises a first curved portion, and the second non-planar portion comprises a second curved portion opposite the first curved portion.

US Patent:

20180258416, Sep 13, 2018

Filed:

Mar 8, 2018

Appl. No.:

15/915909

Inventors:

- Scottsdale AZ, US
Kevin Lin - Gilbert AZ, US
Taraka Sai Pavan Grandhi - Tempe AZ, US

International Classification:

C12N 15/10
B01J 20/291
B01D 15/38

Abstract:

Ligands and methods for selectively binding hypermethylated DNA from a sample. The ligands include a CG-region binding molecule-conjugated resin derived from the aminoglycoside antibiotic amikacin. Furthermore, the CG-region binding molecule may be conjugated to the resin with a crosslinker and/or may be modified with one or more of long chain and short chain alkyl, aryl, piperazinyl, piperidyl, and pyrrolidyl groups. Such ligands are used in methods for contacting a sample to thereby selectively bind hypermethylated DNA.