Kevin D Neilson

US Patent:

7949973, May 24, 2011

Filed:

Apr 3, 2008

Appl. No.:

12/061786

Inventors:

Kevin Marc Neilson - Boulder CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/455

US Classification:

716104, 716106, 703 13

Abstract:

Methods of implementing circuits while automatically taking multi-cycle paths into account. A processor-implemented method can include inputting a behavioral description of the circuit, a simulation test bench for the circuit, and a library that includes at least one synchronous element. The synchronous element includes code that, when simulated, outputs tracking information including a minimum number of clock cycles between state changes for terminals of the synchronous element. The behavioral description is synthesized to generate a netlist description of the circuit. The netlist description includes at least one instance of the synchronous element. The netlist description is simulated using the simulation test bench and the library. The simulation outputs a description of all multi-cycle paths in the netlist description based on the tracking information output by all instances of the synchronous element in the netlist description. This description can provide constraints for use when placing and routing the design.

US Patent:

7739092, Jun 15, 2010

Filed:

Jan 31, 2006

Appl. No.:

11/343554

Inventors:

Jonathan B. Ballagh - Boulder CO, US
L. James Hwang - Menlo Park CA, US
Roger B. Milne - Boulder CO, US
Kevin Marc Neilson - Boulder CO, US
Nabeel Shirazi - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 13, 703 14, 703 20, 703 21, 713 1, 713100, 716 16, 716 17

Abstract:

A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.