Kevin A Robinson

US Patent:

7321132, Jan 22, 2008

Filed:

Mar 15, 2005

Appl. No.:

11/080293

Inventors:

Kevin L. Robinson - Clay NY, US
Larry Witkowski - Plano TX, US
Ming-Yih Kao - Dallas TX, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H01L 29/06
H01L 29/201
H01L 29/732
H01L 21/338

US Classification:

257 12, 257 90, 257 94, 257183, 438167, 438172, 438186, 438191

Abstract:

A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

US Patent:

7488992, Feb 10, 2009

Filed:

Dec 4, 2003

Appl. No.:

10/727387

Inventors:

Kevin L. Robinson - Clay NY, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H01L 29/74
H01L 31/111
H01L 31/0328
H01L 31/0336
H01L 31/072

US Classification:

257130, 257133, 257136, 257194

Abstract:

The present invention comprises an integrated circuit fabricated on a single substrate where the integrated circuit comprises a first block comprising an enhancement mode pHEMT transistor on a substrate; a second block comprising a depletion mode pHEMT transistor on the substrate, the second block operatively connected to the first block; and a third block comprising a power pHEMT transistor on the substrate, the third block operatively connected to at least one of the first block and the second block. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope of meaning of the claims.

US Patent:

7525509, Apr 28, 2009

Filed:

Aug 8, 2006

Appl. No.:

11/500868

Inventors:

Kevin L. Robinson - Clay NY, US

Assignee:

Lockheed Martin - Syracuse NY

International Classification:

H01Q 1/36

US Classification:

343895, 343787

Abstract:

The electrical length of an antenna element is modified by depositing on a top surface of a voltage variable dielectric a first conductor pattern. The identical conductor pattern is also deposited on a bottom surface of the dielectric layer. The dielectric layer is tunable and the structure is a sandwich with two identical conductors on top and bottom of a tunable dielectric area. The sandwich is created in the same shape as a planar spiral or logarithmic spiral and a DC electric field is applied between the conductors that control the dielectric constant and hence the electrical length of the antenna element.

US Patent:

7541232, Jun 2, 2009

Filed:

Nov 28, 2007

Appl. No.:

11/998072

Inventors:

Kevin L. Robinson - Clay NY, US
Larry Witkowski - Plano TX, US
Ming-Yih Kao - Dallas TX, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H01L 21/338
H01L 21/461

US Classification:

438172, 438167, 438169, 438191, 438738, 438740, 257191, 257E21403, 257E21407

Abstract:

A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate recesses in the structure. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

US Patent:

7583176, Sep 1, 2009

Filed:

Mar 8, 2006

Appl. No.:

11/370766

Inventors:

Kevin L. Robinson - Clay NY, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H01H 37/32
H01L 29/08

US Classification:

337167, 337298, 257108, 257 43

Abstract:

A circuit including: at least one conductor; a least one vanadium oxide region electrically coupled to the at least one conductor; and, at least one thermionic cooler thermally coupled to the vanadium oxide region; wherein, the thermionic cooler is suitable for transitioning the at least one vanadium oxide region from a first temperature range where the at least one vanadium oxide region is substantially conductive to a second temperature range where the at least one vanadium oxide region is substantially non-conductive.

US Patent:

7642881, Jan 5, 2010

Filed:

Mar 8, 2006

Appl. No.:

11/371174

Inventors:

Kevin L. Robinson - Clay NY, US
William H. Huber - Scotia NY, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H01P 1/15

US Classification:

333104, 333262, 257108, 257 43

Abstract:

A circuit including: at least one radio frequency microstrip conductor; and, a least one vanadium oxide region electrically coupled to the at least one radio frequency microstrip conductor; wherein, the at least one vanadium oxide region is substantially conductive in a first temperature range, and substantially non-conductive in a second temperature range.

US Patent:

7919855, Apr 5, 2011

Filed:

Feb 21, 2006

Appl. No.:

11/307765

Inventors:

Kevin L. Robinson - Clay NY, US

Assignee:

Lockheed Martin - Bethesda MD

International Classification:

H01L 23/373

US Classification:

257713, 257E2311

Abstract:

A semiconductor device including at least one gate terminal in operational contact with an active layer or top surface of the semiconductor substrate includes a deposited layer of boron phosphide covering the gate terminal and at least a portion of the active layer or the top surface next to and extending from the gate terminal. According to an aspect, the layer of boron phosphide is deposited by a chemical vapor deposition (CVD) process. The boron phosphide layer will have a thickness less than or equal to about 10 microns. The boron phosphide provides a heat spreading coating across the die surface, thus increasing the surface area that conducts the heat from the die. Since the boron phosphide coating is in intimate contact with the gate terminal(s) and the immediately adjacent passivation surfaces of the device, generated heat can rapidly spread away from the active junction or channel. The additional thermal path(s) provided by the boron phosphide coating may terminate away from the active region to further conduct away the heat through thermally unused areas of the device.

US Patent:

7936210, May 3, 2011

Filed:

Feb 12, 2007

Appl. No.:

11/705344

Inventors:

Kevin L. Robinson - Clay NY, US
Paul Saunier - Addison TX, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H01L 25/00

US Classification:

327581, 327566

Abstract:

A traveling wave device employs an active Gallium Nitride FET. The Gallium Nitride FET has a plurality of gate feeding fingers connecting to an input gate transmission line. The FET has a drain electrode connected to an output drain transmission line with the source electrode connected to a point of reference potential. The input and output transmission lines are terminated with terminating impedances which are not matched to the gate and drain transmission lines. The use of Gallium Nitride enables the terminating impedance to be at much higher levels than in the prior art. The use of Gallium Nitride permits multiple devices to be employed, thus resulting in higher gain amplifiers with higher voltage operation and higher frequency operation. A cascode traveling wave amplifier employing GaN FETs is also described having high gain and bandwidth.