Kevin Tran

US Patent:

7058830, Jun 6, 2006

Filed:

Mar 19, 2003

Appl. No.:

10/392764

Inventors:

Sang Hoo Dhong - Austin TX, US
Silvia Melitta Mueller - St. Ingbert, DE
Hwa-Joon Oh - Austin TX, US
Kevin Duc Tran - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/32

US Classification:

713320, 713322, 713323, 713324, 713340, 708490, 708495, 708496, 708497, 708501

Abstract:

The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.

US Patent:

7149877, Dec 12, 2006

Filed:

Jul 17, 2003

Appl. No.:

10/621908

Inventors:

Sang Hoo Dhong - Austin TX, US
Hwa-Joon Oh - Austin TX, US
Brad William Michael - Cedar Park TX, US
Silvia Melitta Mueller - St. Ingbert, DE
Kevin D. Tran - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/76

US Classification:

712 22, 712 2, 712221

Abstract:

A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.

US Patent:

7290023, Oct 30, 2007

Filed:

Nov 20, 2003

Appl. No.:

10/718303

Inventors:

Sang Hoo Dhong - Austin TX, US
Silvia Melitta Mueller - Saarland, DE
Hwa-Joon Oh - Austin TX, US
Kevin D. Tran - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/38

US Classification:

708501

Abstract:

A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value. The exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the first incremented exponent value and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value. Either the exponent output value, the first incremented exponent output value, or the second exponent output value are then selected.

US Patent:

7747847, Jun 29, 2010

Filed:

Mar 27, 2006

Appl. No.:

11/389980

Inventors:

Uri El Zur - Irvine CA, US
Kan Frankie Fan - Diamond Bar CA, US
Murali Rajagopal - Irvine CA, US
Kevin Tran - Tustin CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 15/177

US Classification:

713 2, 709222

Abstract:

Certain aspects of a method for iSCSI boot may include loading boot BIOS code from a host bus adapter or a network interface controller (NIC) by an iSCSI client device. A connection may be established to an iSCSI target by the iSCSI client device after loading the boot BIOS code. The boot BIOS code may be chained to at least one interrupt handler over iSCSI protocol. An operating system may be remotely booted from the iSCSI target by the iSCSI client device based on chaining the interrupt handler. An Internet protocol (IP) address and/or location of the iSCSI target may be received. At least one iSCSI connection may be initiated to the iSCSI target based on chaining at least one interrupt handler. The iSCSI target may be booted in real mode if at least one master boot record is located in the memory.

US Patent:

8321658, Nov 27, 2012

Filed:

Jun 29, 2010

Appl. No.:

12/826075

Inventors:

Uri El Zur - Irvine CA, US
Kan Frankie Fan - Diamond Bar CA, US
Murali Rajagopal - Irvine CA, US
Kevin Tran - Tustin CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 15/177

US Classification:

713 2, 709222

Abstract:

Certain aspects of a method for iSCSI boot may include loading boot BIOS code from a host bus adapter or a network interface controller (NIC) by an iSCSI client device. A connection may be established to an iSCSI target by the iSCSI client device after loading the boot BIOS code. The boot BIOS code may be chained to at least one interrupt handler over iSCSI protocol. An operating system may be remotely booted from the iSCSI target by the iSCSI client device based on chaining the interrupt handler. An Internet protocol (IP) address and/or location of the iSCSI target may be received. At least one iSCSI connection may be initiated to the iSCSI target based on chaining at least one interrupt handler. The iSCSI target may be booted in real mode if at least one master boot record is located in the memory.

US Patent:

20070061553, Mar 15, 2007

Filed:

Nov 1, 2006

Appl. No.:

11/555513

Inventors:

Sang Dhong - Austin TX, US
Hwa-Joon Oh - Austin TX, US
Brad Michael - Cedar Park TX, US
Silvia Mueller - St. Ingbert, DE
Kevin Tran - Austin TX, US

International Classification:

G06F 9/44

US Classification:

712221000, 712223000

Abstract:

A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.

US Patent:

63237040, Nov 27, 2001

Filed:

Aug 8, 2000

Appl. No.:

9/633948

Inventors:

Perry H. Pelley - Austin TX
Kevin Tran - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03K 300

US Classification:

327112

Abstract:

Input and output buffer circuitry (12, 14, 16) is provided which are compatible with busses operating at different voltage levels. The buffer circuitry is self-configuring based on the type of bus to which it is coupled. The buffer circuitry includes voltage level detect circuitry (20) and pad level detect circuitry (28) which can reconfigure driver (34, 54) and level shifter circuits (24, 26) in order to protect the switching devices of the buffers.

US Patent:

20230046164, Feb 16, 2023

Filed:

Jun 3, 2022

Appl. No.:

17/832083

Inventors:

Trung Minh Tran - Round Rock TX, US
Kevin Quang Tran - Round Rock TX, US
Steven Minh Tran - Round Rock TX, US

International Classification:

H01M 10/0525
H01M 50/264
H01M 10/48
H01M 10/44

Abstract:

The present invention is an improved lithium-ion battery core system for use within an electric vehicle. The present invention has a battery receiver and a battery charger. The battery receiver has a battery adaptor and a receiver lock. The battery adaptor allows the present invention to insert standardized lithium-ion cores that are managed at a specified voltage level suitable for the electric vehicle. The lithium-ion core includes a removable and rechargeable lithium-ion core, that can be charged by the battery charger. The battery charger has a plurality of cores, a plurality of lights, and an ejection button. The ejection button removes a battery from the battery charger. All of these various components allow for the present invention to provide users with a system for keeping electric vehicles properly charged for long distance travel.