Kevin J Walker

US Patent:

7743279, Jun 22, 2010

Filed:

Apr 6, 2007

Appl. No.:

11/697428

Inventors:

Kevin R. Walker - Los Gatos CA, US
John H. Mylius - Framingham MA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 11/00

US Classification:

714 30, 712227

Abstract:

In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

US Patent:

7984338, Jul 19, 2011

Filed:

May 5, 2010

Appl. No.:

12/774346

Inventors:

Kevin R. Walker - Los Gatos CA, US
John H. Mylius - Framingham MA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 11/00

US Classification:

714 45

Abstract:

In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

US Patent:

8381041, Feb 19, 2013

Filed:

Jun 10, 2011

Appl. No.:

13/157911

Inventors:

Kevin R. Walker - Los Gatos CA, US
John H. Mylius - Framingham MA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 11/00

US Classification:

714 45

Abstract:

In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

US Patent:

8402314, Mar 19, 2013

Filed:

Dec 9, 2010

Appl. No.:

12/963975

Inventors:

Deniz Balkan - Santa Clara CA, US
Kevin R. Walker - Los Gatos CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 11/00

US Classification:

714 31, 714 27

Abstract:

A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

US Patent:

20120150479, Jun 14, 2012

Filed:

Dec 10, 2010

Appl. No.:

12/965281

Inventors:

Deniz Balkan - Santa Clara CA, US
Kevin R. Walker - Los Gatos CA, US

International Classification:

G06F 19/00

US Classification:

702125

Abstract:

A debug port configured to generate and provide a return clock is disclosed. In one embodiment, an integrated circuit (IC) includes one or more functional units and a debug port (DP). The DP is configured to enable access by an external debugger to the functional unit(s) of the IC for debugging purposes. The DP includes circuitry that may generate a first clock signal that is provided to the functional unit(s) during debug operations. Receiving test result data at the DP may require a return clock signal that is not provided by the functional unit(s). Accordingly, the IC may include a clock modifier coupled to receive the first clock signal. The clock modifier may generate a second clock signal based on the first, the second clock signal being provided to the DP as a return clock signal.

US Patent:

20130159775, Jun 20, 2013

Filed:

Feb 13, 2013

Appl. No.:

13/765920

Inventors:

Apple Inc. - Cupertino CA, US
Kevin R. Walker - Los Gatos CA, US
Mitchell P. Lichtenberg - Sunnyvale CA, US

Assignee:

APPLE INC. - Cupertino CA

International Classification:

G06F 11/26

US Classification:

714 34

Abstract:

A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

US Patent:

20140052929, Feb 20, 2014

Filed:

Aug 20, 2012

Appl. No.:

13/590150

Inventors:

Manu Gulati - Saratoga CA, US
James D. Ramsay - San Jose CA, US
Kevin R. Walker - Los Gatos CA, US

International Classification:

G06F 12/08

US Classification:

711141, 711E12033

Abstract:

A system and method for efficiently monitoring traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes multiple bus event filters. Programmable configuration registers are used to assign the bus event filters to selected buses for monitoring associated bus traffic and determining whether qualified bus events occur. If so, the bus event filters increment an associated count for each of the qualified bus events. The values used for determining qualified bus events may be set by programmable configuration registers.

US Patent:

20140052930, Feb 20, 2014

Filed:

Aug 20, 2012

Appl. No.:

13/590159

Inventors:

Manu Gulati - Saratoga CA, US
James D. Ramsay - San Jose CA, US
Kevin R. Walker - Los Gatos CA, US

International Classification:

G06F 12/08
G06F 11/22

US Classification:

711141, 714 45, 714E11145, 711E12033

Abstract:

A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes a trace buffer with multiple physical partitions assigned to subsets of the multiple buses. The number of partitions is less than the number of multiple buses. One or more trace instructions may cause a trace history, trace bus event statistics, local time stamps and a global time-base value to be stored in a physical partition within the trace buffer.