Kevin Doug Walker

Address:

14500 Umpire St, Brighton, CO 80603

VIN:

2FMDK49C97BB38754

Make:

FORD

Model:

EDGE

Year:

2007

US Patent:

8509727, Aug 13, 2013

Filed:

Jun 30, 2005

Appl. No.:

11/173369

Inventors:

Brad Medford - Austin TX, US
Kevin B. Walker - Oswego IL, US
Robert B. Hill - Spring Branch TX, US
Thomas Scott Webster - San Antonio TX, US

Assignee:

AT&T Intellectual Property I, L.P. - Atlanta GA

International Classification:

H04M 11/04
H04N 7/167
H04N 7/173

US Classification:

4554041, 725 33, 725108

Abstract:

A system and method for providing Emergency Alert System (EAS) notifications over Internet Protocol (IP) delivery platforms, including a proxy server coupled to an emergency alert system receiver, a subscriber management database coupled to the proxy server, and an instant messaging server coupled to the proxy server and to the subscriber management server.

US Patent:

52273261, Jul 13, 1993

Filed:

Jun 3, 1992

Appl. No.:

7/894171

Inventors:

Kevin L. Walker - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2170

US Classification:

437 52

Abstract:

The method is provided for selectively fabricating erasable read-only memory and read-only memory cells at a face of a layer of semiconductor of a first conductivity type. Active areas on the face of the layer of semiconductor are selectively defined by masking the face of the layer of semiconductor and patterning and etching the mask to expose first and second areas of the layer of semiconductor. A layer of conductor is formed insulatively adjacent the active area of each cell being fabricated. The layer of conductor is patterned and etched to define a first level gate conductor adjacent at least a portion of the active area of each cell being fabricated, the first level gate of each read-only memory cell set to a logic zero being fabricated disposed adjacent a one of the insulator regions adjacent a corresponding one of the third exposed areas. A layer of interlevel insulator is formed adjacent the first level gate of each erasable read-only memory cell being fabricated. A second layer of conductor is formed adjacent the layer of interlevel insulator of each erasable memory cell being fabricated.