Kevin C Walker

US Patent:

52273261, Jul 13, 1993

Filed:

Jun 3, 1992

Appl. No.:

7/894171

Inventors:

Kevin L. Walker - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2170

US Classification:

437 52

Abstract:

The method is provided for selectively fabricating erasable read-only memory and read-only memory cells at a face of a layer of semiconductor of a first conductivity type. Active areas on the face of the layer of semiconductor are selectively defined by masking the face of the layer of semiconductor and patterning and etching the mask to expose first and second areas of the layer of semiconductor. A layer of conductor is formed insulatively adjacent the active area of each cell being fabricated. The layer of conductor is patterned and etched to define a first level gate conductor adjacent at least a portion of the active area of each cell being fabricated, the first level gate of each read-only memory cell set to a logic zero being fabricated disposed adjacent a one of the insulator regions adjacent a corresponding one of the third exposed areas. A layer of interlevel insulator is formed adjacent the first level gate of each erasable read-only memory cell being fabricated. A second layer of conductor is formed adjacent the layer of interlevel insulator of each erasable memory cell being fabricated.