Kevin A Walker

US Patent:

7743279, Jun 22, 2010

Filed:

Apr 6, 2007

Appl. No.:

11/697428

Inventors:

Kevin R. Walker - Los Gatos CA, US
John H. Mylius - Framingham MA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 11/00

US Classification:

714 30, 712227

Abstract:

In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

US Patent:

7984338, Jul 19, 2011

Filed:

May 5, 2010

Appl. No.:

12/774346

Inventors:

Kevin R. Walker - Los Gatos CA, US
John H. Mylius - Framingham MA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 11/00

US Classification:

714 45

Abstract:

In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

US Patent:

7985005, Jul 26, 2011

Filed:

Mar 6, 2007

Appl. No.:

11/715071

Inventors:

Clayton Alexander - Westlake CA, US
Todd Metlen - Ojai CA, US
Doug Botos - San Diego CA, US
Jesse Melrose - San Diego CA, US
Kevin Walker - Raleigh NC, US

Assignee:

Journée Lighting, Inc. - Westlake Village CA

International Classification:

F21V 29/00

US Classification:

362294, 36224902, 362373, 36224911

Abstract:

A light module is removably coupleable to a light fixture and includes an LED lighting element mounted on a mounting base that is operatively coupled to a housing. The light module also includes one or more resilient members that operatively couple the mounting base to the housing and allow the mounting base and housing to resiliently move relative to each other. The resilient members compress when the light module is removably coupled to the light fixture to exert a generally axial force on the mounting base to drive the mounting base into resilient contact with a surface of the light fixture to provide a thermal coupling between the light module and the light fixture.

US Patent:

8381041, Feb 19, 2013

Filed:

Jun 10, 2011

Appl. No.:

13/157911

Inventors:

Kevin R. Walker - Los Gatos CA, US
John H. Mylius - Framingham MA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 11/00

US Classification:

714 45

Abstract:

In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

US Patent:

8402314, Mar 19, 2013

Filed:

Dec 9, 2010

Appl. No.:

12/963975

Inventors:

Deniz Balkan - Santa Clara CA, US
Kevin R. Walker - Los Gatos CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 11/00

US Classification:

714 31, 714 27

Abstract:

A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

US Patent:

8509727, Aug 13, 2013

Filed:

Jun 30, 2005

Appl. No.:

11/173369

Inventors:

Brad Medford - Austin TX, US
Kevin B. Walker - Oswego IL, US
Robert B. Hill - Spring Branch TX, US
Thomas Scott Webster - San Antonio TX, US

Assignee:

AT&T Intellectual Property I, L.P. - Atlanta GA

International Classification:

H04M 11/04
H04N 7/167
H04N 7/173

US Classification:

4554041, 725 33, 725108

Abstract:

A system and method for providing Emergency Alert System (EAS) notifications over Internet Protocol (IP) delivery platforms, including a proxy server coupled to an emergency alert system receiver, a subscriber management database coupled to the proxy server, and an instant messaging server coupled to the proxy server and to the subscriber management server.

US Patent:

20120150479, Jun 14, 2012

Filed:

Dec 10, 2010

Appl. No.:

12/965281

Inventors:

Deniz Balkan - Santa Clara CA, US
Kevin R. Walker - Los Gatos CA, US

International Classification:

G06F 19/00

US Classification:

702125

Abstract:

A debug port configured to generate and provide a return clock is disclosed. In one embodiment, an integrated circuit (IC) includes one or more functional units and a debug port (DP). The DP is configured to enable access by an external debugger to the functional unit(s) of the IC for debugging purposes. The DP includes circuitry that may generate a first clock signal that is provided to the functional unit(s) during debug operations. Receiving test result data at the DP may require a return clock signal that is not provided by the functional unit(s). Accordingly, the IC may include a clock modifier coupled to receive the first clock signal. The clock modifier may generate a second clock signal based on the first, the second clock signal being provided to the DP as a return clock signal.

US Patent:

20130159775, Jun 20, 2013

Filed:

Feb 13, 2013

Appl. No.:

13/765920

Inventors:

Apple Inc. - Cupertino CA, US
Kevin R. Walker - Los Gatos CA, US
Mitchell P. Lichtenberg - Sunnyvale CA, US

Assignee:

APPLE INC. - Cupertino CA

International Classification:

G06F 11/26

US Classification:

714 34

Abstract:

A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.