Kewei Te Yang

US Patent:

6469988, Oct 22, 2002

Filed:

Jul 8, 1999

Appl. No.:

09/349832

Inventors:

Kewei Yang - San Jose CA
Feng Cheng Lin - Union City CA
Yang Jing Ke - Union City CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

H04B 320

US Classification:

370289, 370296, 375220, 375346

Abstract:

Signal processing techniques are applied to data rates at state-of-the-art circuit speeds (presently 1. 6 Gbit/sec) by carrying out the signal flow graph of a cannonical FIR filter algorithm using hybrid analog and digital circuit techniques. A plurality of digital to analog converters (DACs) generate analog currents that are the analogue of the tap coefficients of the FIR filter model. The DACs are used as programmable current sources for the tail current sources of respective differential pair stages. Differential delay signals that are the analogue of the FIR delay-line tap signals are connected to the inputs of respective ones of the differential pair stages. The drains of the input devices of the differential pair stages are connected in parallel to common complementary load circuits. The delay signals act to steer the tap coefficient currents to one or the other of the common load circuits. The parallel connection to common load circuits acts to sum the currents sunk (if any) by each of the commonly connected input devices.

US Patent:

6865503, Mar 8, 2005

Filed:

Dec 24, 2002

Appl. No.:

10/330797

Inventors:

George Harper - Weston MA, US
Mark L. Erlenborn - Naperville IL, US
Keith A Kind - Mission Viejo CA, US
Welborn R Malpass - Evergreen CO, US
Sam L. Spencer - San Diego CA, US
Kewei Yang - San Jose CA, US
Jeff R. Gemar - Superior CO, US

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G06F019/00
G01R031/303

US Classification:

702122, 702120, 324754, 324763, 324765, 714733

Abstract:

State of test points on an integrated circuit are encapsulated in a telemetry frame that is wirelessly conveyed to a test system. Test points may be logic levels or analog levels converted into representative multi-bit values. Conveyance off the circuit may be by radio frequency or optical emission.

US Patent:

7028134, Apr 11, 2006

Filed:

Dec 28, 2000

Appl. No.:

09/750629

Inventors:

Yuanlong Wang - San Jose CA, US
Kewei Yang - San Jose CA, US
Daniel Fu - Sunnyvale CA, US
Feng Cheng Lin - Union City CA, US

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G06F 13/00

US Classification:

710317, 710316, 370360

Abstract:

Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.

US Patent:

7049632, May 23, 2006

Filed:

Dec 24, 2002

Appl. No.:

10/330798

Inventors:

Jeff R. Gemar - Superior CO, US
Mark J. Erlenborn - Naperville IL, US
George Harper - Weston MA, US
Keith A. Kind - Mission Viejo CA, US
Welborn R. Malpass - Evergreen CO, US
Sam L. Spencer - San Diego CA, US
Kewei Yang - San Jose CA, US

Assignee:

Mindspeed Technologies, Inc. - Newport Beach CA

International Classification:

H01L 23/58

US Classification:

257 48, 257 88

Abstract:

Optical transducers disposed on an integrated circuit correspond to test points thereon. The state of optical transducers perceived by an optical sensor is correlated to test points. Alignment of the optical sensor relative to the optical transducers is accomplished electronically or mechanically.

US Patent:

7327732, Feb 5, 2008

Filed:

Nov 27, 2002

Appl. No.:

10/307015

Inventors:

Mark J Erlenborn - Naperville IL, US
Jeff R. Gemar - Superior CO, US
George Harper - Weston MA, US
Kewei Yang - San Jose CA, US
Welborn R Malpass - Evergreen CO, US
Sam L Spencer - San Diego CA, US
Keith A Kind - Mission Viejo CA, US

Assignee:

Mindspeed Technologies, Inc. - Newport Beach CA

International Classification:

H04L 12/28
H04J 3/24

US Classification:

370392, 3703951, 370468, 370474

Abstract:

Incoming bit stream is processed by a single state machine into a circular buffer. Circular buffer accumulates subunits of data to form a major data unit. State machine recognizes the start of major data unit and flags the location of the major data unit in the circular buffer.

US Patent:

7602806, Oct 13, 2009

Filed:

Dec 7, 2004

Appl. No.:

11/005686

Inventors:

Kewei Yang - Saratoga CA, US
Jianbin Hao - San Jose CA, US
Fei Yao - San Jose CA, US
Ning Zhu - San Jose CA, US

Assignee:

Analogix Semiconductor, Inc. - Santa Clara CA

International Classification:

H04L 12/28
H04J 3/16
H04B 1/66

US Classification:

370465, 3703951, 370469, 370419, 375240

Abstract:

Signaling and coding methods and apparatus for long-range 10 and 100 mbps Ethernet transmission. In accordance with the method, a physical layer (PHY) device is provided that includes the long-range capabilities. In operation, the PHY measures the distance to a companion PHY, and if it is within the specification limits, communicates with the companion device in the normal way. If the distance is above the specification limits, the PHY checks to see if the companion PHY is similarly enabled, and if so, switches to a long-range signaling method. In a preferred embodiment, NRZ coding with pre-emphasis on the first bit of two or more bits of the same value is used for a first range exceeding the specification limit, and PAM4 coding is used for a second range exceeding the first range. Various embodiments are disclosed.

US Patent:

20030110338, Jun 12, 2003

Filed:

Dec 6, 2001

Appl. No.:

10/010132

Inventors:

Yuanlong Wang - San Jose CA, US
Kewei Yang - San Jose CA, US

International Classification:

G06F013/14

US Classification:

710/305000

Abstract:

Method and apparatus for receiving bus signals from a first computer module, converting those bus signals into a first point-to-point link and directing the first point-to-point link to a bus emulator. The bus emulator propagates data transfer cycles arriving by the first point-to-point link to a second point-to-point link. The second point-to-point link carries data transfer cycles to a second computer module. The second point-to-point link is converted back into bus signals that interface with the second computer module.

US Patent:

6418537, Jul 9, 2002

Filed:

Jul 8, 1999

Appl. No.:

09/350414

Inventors:

Kewei Yang - San Jose CA
Feng Cheng Lin - Union City CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G06F 104

US Classification:

713400, 713503, 710 60

Abstract:

In a preferred embodiment, the invention uses an 8-to-1 data serialization circuit in the transmitter to convert 80-bit parallel 200 MHz data to 10-bit parallel 1. 6 Mb/s date. On the receiver side, data are captured using a forwarded clock and de-serialized. A single global DLL generates 16 master phases without reference to the word boundaries of data being transmitted. These 16 unreferenced phases are input to a phase rotator that, via a series of calibration steps, maps the unreferenced phases into named phases, and in doing so references the phases to the word boundary of the data being transmitted over the slowest data line of the parallel channel. The named phases are then input to a data interpolator in each receiver, which generates 16 local phases. The 16 local phases correspond to the data-bit centers and data-bit edges for each of the 8 bits transferred per major channel clock period. In a bit-centering calibration step, a training pattern is evaluated by each receiver and each data interpolator dynamically adjusts a delay applied to the 16 local phases to establish the local center-data phases in the center of the bits received by the corresponding receiver.