Khanh Q Tran

US Patent:

6351013, Feb 26, 2002

Filed:

Jul 13, 1999

Appl. No.:

09/352339

Inventors:

Scott Luning - San Francisco CA
David Wu - San Jose CA
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 31062

US Classification:

257368, 257372, 257900, 257369, 438595

Abstract:

The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

US Patent:

6492258, Dec 10, 2002

Filed:

Jun 14, 2001

Appl. No.:

09/881831

Inventors:

Minh Van Ngo - Union City CA
Paul R. Besser - Sunnyvale CA
Matthew Buynoski - Palo Alto CA
John Caffall - San Carlos CA
Nick Maccrae - San Jose CA
Richard J. Huang - Cupertino CA
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438622, 438623, 438625, 438648, 438656, 438688, 257765, 257763, 257764

Abstract:

A method for making 0. 25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

US Patent:

6607962, Aug 19, 2003

Filed:

Aug 9, 2001

Appl. No.:

09/925945

Inventors:

Viktor Zekeriya - Atherton CA
Khanh Tran - Milpitas CA

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 2120

US Classification:

438384, 438382, 438597, 438672, 438675

Abstract:

A method of forming a thin film resistor contact incorporates an etch-stop material to protect the underlying thin film resistor from a subsequent dry etching process to form a contact opening to the thin film resistor. More specifically, the method includes forming a thin film resistor, forming a first dielectric layer over the thin film resistor, forming a first opening through the first dielectric layer to expose an underlying portion of the thin film resistor, forming an etch-stop within the first opening of the first dielectric layer, forming a second dielectric layer over the etch-stop and the first dielectric layer, forming a second opening through the second dielectric layer to expose the underlying portion of the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in electrical contact with the thin film resistor by way of the etch-stop. Alternatively, in the case of an insulating etch-stop, the second opening through the dielectric layer is through the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in direct electrical contact with the thin film resistor.

US Patent:

58888985, Mar 30, 1999

Filed:

Oct 23, 1997

Appl. No.:

8/956588

Inventors:

Minh V. Ngo - Union City CA
Khanh Q. Tran - San Jose CA
Terri J. Kitson - San Jose CA
Lu You - Santa Clara CA
Simon S. Chan - Saratoga CA
Jean Y. Yang - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438622

Abstract:

A patterned metal layer is gap filled with HSQ, an oxide formed thereon by PECVD, e. g. , silicon dioxide derived from silane and N. sub. 2 O, and planarized. The dielectric constant of the HSQ layer is minimized by baking the deposited HSQ layer in an inert atmosphere, e. g. , N. sub. 2, before heat soaking in an N. sub. 2 O-containing atmosphere for no more than about 10 seconds and subsequent PECVD.

US Patent:

63297183, Dec 11, 2001

Filed:

Jun 26, 1998

Appl. No.:

9/105775

Inventors:

Minh Van Ngo - Union City CA
Paul R. Besser - Sunnyvale CA
Matthew Buynoski - Palo Alto CA
John Caffall - San Carlos CA
Nick MacCrae - San Jose CA
Richard J. Huang - Cupertino CA
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348
H01L 2352

US Classification:

257765

Abstract:

A method for making 0. 25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

US Patent:

58889116, Mar 30, 1999

Filed:

Oct 23, 1997

Appl. No.:

8/956590

Inventors:

Minh V. Ngo - Union City CA
Khanh Q. Tran - San Jose CA
Lu You - Santa Clara CA
Jean Y. Yang - Palo Alto CA
Richard J. Huang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21316

US Classification:

438788

Abstract:

Patterned metal layers are gap filled with HSQ and heat soaked in an oxidizing environment prior to oxide deposition by PECVD and planarization. Heat soaking is confined to less than about 10 seconds to minimize the dielectric constant of the HSQ layer.