Khoi V Dinh

US Patent:

7113430, Sep 26, 2006

Filed:

May 31, 2002

Appl. No.:

10/158991

Inventors:

Alexander Hoefler - Round Rock TX, US
Khoi V. Dinh - Austin TX, US
Robert A. Jensen - Austin TX, US
Matthew B. Rutledge - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 16/08

US Classification:

36518523, 36518529, 36518518

Abstract:

A device for reducing the effects of leakage current within electronic devices is disclosed. In one form, a high voltage driver includes a high voltage source coupled to at least one high voltage transistor and a leakage offset module coupled to at least a portion of one of the high voltage transistors. The leakage offset module includes a diode connected MOS device operable to generate an offset voltage and an MOS shunting device coupled in a parallel with the diode connected MOS device. During operation, the diode connected MOS device generates an offset voltage based on a sub-threshold leakage associated with using the high voltage source and the MOS shorting device is operable to short the diode connected MOS device when sub-threshold leakage current is relatively low.

US Patent:

53654790, Nov 15, 1994

Filed:

Mar 3, 1994

Appl. No.:

8/206446

Inventors:

Loc B. Hoang - San Jose CA
Khoi V. Dinh - San Jose CA
Jitendra R. Kulkarni - Mountain View CA

Assignee:

National Semiconductor Corp. - Santa Clara CA

International Classification:

G11C 1140

US Classification:

36518929

Abstract:

A novel row decoder/driver circuit in which switched bias voltages are applied to the bulk regions in order to minimize the maximum voltage differential appearing across transistor devices. This allows the decoder/driver circuit to be conveniently fabricated and designed to allow normal transistors rather than more complex and expensive high voltage transistors, to form the row decoder/driver. The bulk regions containing the pull-up and pull-down transistors are biased by voltages which are switched during erasure depending on whether the row line is selected or deselected in order to assure that excessive voltages do not appear across based upon the voltage levels applied to the transistors.

US Patent:

60761709, Jun 13, 2000

Filed:

Sep 16, 1996

Appl. No.:

8/711517

Inventors:

Khoi Van Dinh - Austin TX
Clinton Thomas Glover - Austin TX
Matthew Russell Nixon - Austin TX

Assignee:

Motorola - Schaumburg IL

International Classification:

G06F 104

US Classification:

713500

Abstract:

In a data processing system, a memory control unit (22) provides a control register bit field (60), logic, and a state machine (62) which facilitate a programmable number of clocks for an initial access to an on-chip memory (20). Specifically, the memory control unit (22) allows an external user to modify memory control signals to provide consistent access times across different frequencies of the system clock and allows memory control signals to be modified to optimize access time dynamically. Also, programmable control of the control signals to the memory (20) allows the memory to operate at system clock frequencies which are higher than expected.

US Patent:

58019871, Sep 1, 1998

Filed:

Mar 17, 1997

Appl. No.:

8/818273

Inventors:

Khoi Van Dinh - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 1134

US Classification:

36518518

Abstract:

Clock frequency and number of stages of a charge pump for nonvolatile memories are automatically adjusted to compensate for lower efficiency due to lower power supply, higher temperature, or weaker process. A low voltage detector will cause the charge pump to increase the charge pump's clock frequency and number of stages when a low voltage is detected, making the charge pump's capability constant over a voltage range. A counter timing programming/erasing time will cause the charge pump clock frequency and number of stages to increase when the programming/erasing time exceeds certain thresholds. This boosts the charge pump's drivability for a weaker process, higher temperature, or aged cells.