Kin Keung Chan

US Patent:

6446170, Sep 3, 2002

Filed:

Jan 19, 1999

Appl. No.:

09/232239

Inventors:

Kin Shing Chan - Austin TX
Dwain Alan Hicks - Pflugerville TX
Michael John Mayfield - Austin TX
Shih-Hsiung Stephen Tung - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711132, 711133, 711210

Abstract:

A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit. One embodiment of the invention further includes accessing the cache, in a first miss access, with the first operation from the miss latch in response to a cache miss that resulted from the first cache access. In a presently preferred embodiment, a second access is executed to access the cache with a second operation queued in the stack in response to a cache hit resulting from the first cache access.

US Patent:

62984357, Oct 2, 2001

Filed:

Apr 16, 1996

Appl. No.:

8/633267

Inventors:

Kin Shing Chan - Austin TX
Hung Qui Le - Austin TX
Dung Quoc Nguyen - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 930

US Classification:

712217

Abstract:

A method and apparatus for increasing instruction level parallelism using a buffer pointer assignment scheme is implemented whereby rename buffers are assigned during dispatch even though the physical rename registers may not yet be available. These virtual rename buffers are assigned by a buffer pointer assignment table. A virtual bit implemented along with each of the physical rename registers is flipped when an instruction corresponding to the entry stored within a particular physical rename register is completed and the result written to the architected register. Thus, at dispatch time, rename registers are assigned as if there were more rename buffers than there existed physical rename registers.

US Patent:

58092684, Sep 15, 1998

Filed:

Jun 29, 1995

Appl. No.:

8/496833

Inventors:

Kin Chan - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

395376

Abstract:

A method and system are disclosed for tracking the allocation of resources within a processor having multiple execution units which support speculative execution of instructions. The processor includes a resource counter including a first counter and a second counter and a number of resources, wherein one or more of the resources are allocated to each of a number of instructions dispatched for execution to the execution units. In response to dispatching an instruction among the plurality of instructions to one of the execution units for execution, the first counter is incremented once for each of the resources allocated to the instruction, and if the instruction is a first instruction within a speculative execution path, the second counter is loaded with a value of the first counter prior to incrementing the first counter. In response to completion of a particular instruction among the number of instructions dispatched to one of the multiple execution units, the first and the second counters are decremented once for each resource allocated to the particular instruction. In response to a refutation of the speculative execution path, a value of the second counter is transferred to the first counter, such that the resource counter tracks a number of the plurality of resources allocated to the plurality of instructions.

US Patent:

62984179, Oct 2, 2001

Filed:

Nov 20, 1998

Appl. No.:

9/196906

Inventors:

Kin Shing Chan - Austin TX
Dwain Alan Hicks - Pflugerville TX
Michael John Mayfield - Austin TX
Shih-Hsiung Stephen Tung - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711143

Abstract:

A deallocation pipelining circuit for use in a cache memory subsystem. The pipelining circuit is configured to initiate a storeback buffer (SBB) transfer of first line data stored in a first line of a cache memory array if the deallocation pipelining circuit detects a cache miss signal corresponding to the first line and identifies the first line data as modified data. The deallocation pipelining circuit is configured to issue a storeback request signal to a bus interface unit after the completion of the SBB transfer. The circuit initiates a bus interface unit transfer of the first line data after receiving a data acknowledge signal from the bus interface unit. The pipelining circuit is still further configured to deallocate the first line of the cache memory after receiving a request acknowledge signal from the bus interface unit. This deallocation of the first line of the cache memory occurs regardless of a completion status of the bus interface unit transfer whereby a pending fill of the first cache line may proceed prior to completion of the bus interface unit transfer. In one embodiment, the storeback buffer includes first and second segments for storing first and second segment data respectively.

US Patent:

59742402, Oct 26, 1999

Filed:

Jun 7, 1995

Appl. No.:

8/480999

Inventors:

Kin Shing Chan - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 938

US Classification:

395394

Abstract:

In response to dispatching a condition register modifying instruction to an execution unit, a condition register rename buffer is associated with such a condition register modifying instruction. The instruction is then executed in the execution unit. Following the execution of the condition register modifying instruction, condition register data is set in the condition register rename buffer to reflect the result of such instruction execution. Additionally, an indicator is set to indicate the condition register data is valid. At the time for completing the condition register modifying instruction, the condition register data is transferred from the condition register rename buffer to the architected condition register, thereby permitting condition register modifying instructions to be dispatched, executed, and finished before the condition register is available to complete each condition register modifying instruction.

US Patent:

62021281, Mar 13, 2001

Filed:

Mar 11, 1998

Appl. No.:

9/038422

Inventors:

Kin Shing Chan - Austin TX
Dwain Alan Hicks - Pflugerville TX
Peichun Peter Liu - Austin TX
Michael John Mayfield - Austin TX
Shih-Hsiung Stephen Tung - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711131

Abstract:

An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration. An existing Real Address (RA) cache snoop port is used to check whether a pre-fetching stream's line access is a true cache hit or not.

US Patent:

57779180, Jul 7, 1998

Filed:

Feb 13, 1996

Appl. No.:

8/600691

Inventors:

Kin Shing Chan - Austin TX
Chiao-Mei Chuang - Cupertino CA
Sang Hoo Dhong - Austin TX
Alessandro Marchioro - Ferney-Voltaire, FR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 750

US Classification:

36478604

Abstract:

A fast adder/subtracter using a decoder and shifting function instead of conventional full-adders is disclosed. The circuit is optimized for the addition of multiple operands up to 4-5 binary bits in magnitude. Using this method a subtraction operation can be performed at no added cost with respect to addition (compared to the conventional method requiring complementing one of the operands). Addition and subtraction of multiple operands is implemented by simple multiple shift operations. The multiple shift operations can be implemented as a chain of series NMOS pulldown devices with a precharged load providing considerable speed advantage over conventional solutions. Fast overflow detection may be implemented by or-ing the higher order bits in the shifter.

US Patent:

61856746, Feb 6, 2001

Filed:

Apr 5, 1995

Appl. No.:

8/417421

Inventors:

Kin Shing Chan - Austin TX
Chiao-Mei Chuang - Cupertino CA
Alessandro Marchioro - Ferney Voltaire, FR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

712230

Abstract:

A computer processing unit is provided that includes an apparatus for generating an address of the next instruction to be completed. The apparatus includes a first table for storing a plurality of entries each corresponding to a dispatched instruction, each entry comprising an identifier that identifies the corresponding instruction and a status bit that indicates if the corresponding instruction is completed; a second table for storing a plurality of entries each corresponding to dispatched branch instructions, each entry comprising the same identifier stored in the first table, a target address of the dispatched branch instruction and a resolution status field that indicates at least if the corresponding branch instruction has been resolved taken or has been resolved not taken; program counter update logic that, in each machine cycle, updates a program counter to store and output the address of the next instruction to be completed according to the entries stored in the first table and the second table. Because the first and second tables employ efficient identification tags to identify instructions that modify the control flow of the execution pipeline and the target address of such instructions, the computer processing unit of the present invention need not store the full address of each instruction in the execution pipeline to update the program counter as is conventional, and thus saves real estate that may be used for other circuitry.