Kiran K Bondalapati

US Patent:

7840780, Nov 23, 2010

Filed:

Apr 4, 2008

Appl. No.:

12/098303

Inventors:

William A. Hughes - San Jose CA, US
Kiran K. Bondalapati - Los Altos CA, US
Philip E. Madrid - Austin TX, US
Stephen C. Ennis - Austin TX, US

Assignee:

Globalfoundries Inc. - Grand Cayman

International Classification:

G06F 9/00

US Classification:

712 30, 712 28

Abstract:

In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e. g. a chip multiprocessor).

US Patent:

8195887, Jun 5, 2012

Filed:

Jan 21, 2009

Appl. No.:

12/356624

Inventors:

William A. Hughes - San Jose CA, US
Kiran K. Bondalapati - Los Altos CA, US
Kevin M. Lepak - Austin TX, US
Benjamin T. Sander - Austin TX, US

International Classification:

G06F 12/08
G06F 1/32

US Classification:

711135, 713323

Abstract:

A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.

US Patent:

8442786, May 14, 2013

Filed:

Jun 2, 2010

Appl. No.:

12/792308

Inventors:

Samuel D. Naffziger - Fort Collins CO, US
John P. Petry - San Diego CA, US
Kiran K. Bondalapati - Los Altos CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G01R 21/00
G06F 1/00

US Classification:

702 62, 713340

Abstract:

A system and method for efficient reporting of power usage. A power reporting unit within a processor receives a power consumption number once every sample interval from a power monitor. The power monitor determines a power consumption number based on sampled signals within one or more functional blocks in the processor, rather than based on temperature. An average power consumption number is computed based on received power consumption numbers for a running time interval, wherein the running time interval is larger than the sample interval. This value is conveyed to an external agent. Responsive to receiving and processing the average power consumption number, the external agent may cause changes in a cooling system.

US Patent:

8595563, Nov 26, 2013

Filed:

Jul 18, 2011

Appl. No.:

13/184982

Inventors:

Benjamin Tsien - Fremont CA, US
Kiran Bondalapati - Los Altos CA, US
Hao Huang - Austin TX, US
William A. Hughes - San Jose CA, US
Eric Rentschler - Steamboat Springs CO, US
Jeremy Schreiber - Austin TX, US
Aaron J. Grenat - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 11/00

US Classification:

714 45, 714 35

Abstract:

Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.

US Patent:

7996653, Aug 9, 2011

Filed:

Oct 7, 2010

Appl. No.:

12/899979

Inventors:

William A. Hughes - San Jose CA, US
Kiran K. Bondalapati - Los Altos CA, US
Philip E. Madrid - Austin TX, US
Stephen C. Ennis - Austin TX, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

G06F 9/30

US Classification:

712 28

Abstract:

In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e. g. a chip multiprocessor).

US Patent:

20110289332, Nov 24, 2011

Filed:

May 24, 2010

Appl. No.:

12/786143

Inventors:

Kiran Bondalapati - Los Altos CA, US
William Alexander Hughes - San Jose CA, US
Ming So - Danville CA, US
Xiaogang Zheng - Sunnyvale CA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 1/26

US Classification:

713323, 713340

Abstract:

Techniques for power management in a multi-processor system are disclosed. One of the processors in the system monitors whether all threads on all central processing unit (CPU) cores in the multi-processor system halt, and send a message to a south bridge to cause at least a part of the system to enter a low power state if all threads in the multi-processor system halt. The processor sends another message to the south bridge to cause at least a part of the multi-processor system to wake up if at least one thread on any CPU core in the multi-processor system exits a halt.

US Patent:

20110296412, Dec 1, 2011

Filed:

May 25, 2011

Appl. No.:

13/115354

Inventors:

Gaurav Banga - Cupertino CA, US
Ian Pratt - Cambridge, GB
Kiran Bondalapati - Los Altos CA, US
Vikram Kapoor - Cupertino CA, US

International Classification:

G06F 9/455

US Classification:

718 1

Abstract:

Approaches for executing untrusted software on a client without compromising the client using micro-virtualization to execute untrusted software in isolated contexts. A template for instantiating a virtual machine on a client is identified in response to receiving a request to execute an application. After the template is identified, without human intervention, a virtual machine is instantiated, using the template, in which the application is to be executed. The template may be selected from a plurality of templates based on the nature of the request, as each template describe characteristics of a virtual machine suitable for a different type of activity. Selected resources such as files are displayed to the virtual machines according to user and organization policies and controls. When the client determines that the application has ceased to execute, the client ceases execution of the virtual machine without human intervention.

US Patent:

20120144215, Jun 7, 2012

Filed:

Dec 3, 2010

Appl. No.:

12/960095

Inventors:

Samuel D. Naffziger - Fort Collins CO, US
John P. Petry - San Diego CA, US
Kiran Bondalapati - Los Altos CA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 1/32
G06F 1/26

US Classification:

713320, 713340

Abstract:

The maximum current is limited in a multi-processor core system by monitoring the latest power consumption in the processor cores, in order to prevent a system shutdown as a result of an over-current event. If the sum of the latest power of the processor cores exceeds a threshold limit, a performance state (P-state) limit is enforced in the processor cores. The P-state limit causes a P-state change to a lower frequency, voltage and thus a lower current.