Kulwant Singh Egan

US Patent:

59111097, Jun 8, 1999

Filed:

Feb 13, 1997

Appl. No.:

8/800012

Inventors:

Reda R. Razouk - Sunnyvale CA
Kulwant S. Egan - San Jose CA
Wipawan Yindeepol - San Jose CA
Waclaw C. Koscielniak - Santa Clara CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 2162

US Classification:

438424

Abstract:

A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.

US Patent:

55811108, Dec 3, 1996

Filed:

Aug 17, 1995

Appl. No.:

8/516114

Inventors:

Reda R. Razouk - Sunnyvale CA
Kulwant S. Egan - San Jose CA
Wipawan Yindeepol - San Jose CA
Waclaw C. Koscielniak - Santa Clara CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 2712

US Classification:

257513

Abstract:

A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.

US Patent:

63296985, Dec 11, 2001

Filed:

Sep 21, 1999

Appl. No.:

9/399911

Inventors:

Waclaw C. Koscielniak - Santa Clara CA
Kulwant S. Egan - San Jose CA
Jayasimha S. Prasad - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01K 27082

US Classification:

257565

Abstract:

An improved method and an apparatus for forming a self-aligned epitaxial base bipolar transistor in a semiconductor material is disclosed. The method of the invention involves forming an intrinsic base region formed by growing an epitaxial semiconductor material over a collector region. A raised sacrificial emitter core is then formed on the intrinsic base region followed by depositing a substantially conformal spacer layer over the sacrificial emitter core. Next, the spacer material is anisotropically etched such that a protective spacer ring is formed about the sacrificial emitter core. An extrinsic base is then formed by implanting dopant into the epitaxial base region wherein the sacrificial emitter core and the spacer ring preserve an emitter region. The spacer ring also serves to self-align the extrinsic base region to the emitter region. The protective sacrificial emitter core and spacer ring are then removed.

US Patent:

60202467, Feb 1, 2000

Filed:

Mar 13, 1998

Appl. No.:

9/042430

Inventors:

Waclaw C. Koscielniak - Santa Clara CA
Kulwant S. Egan - San Jose CA
Jayasimha S. Prasad - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21331

US Classification:

438341

Abstract:

An improved method and an apparatus for forming a self-aligned epitaxial base bipolar transistor in a semiconductor material is disclosed. The method of the invention involves forming an intrinsic base region formed by growing an epitaxial semiconductor material over a collector region. A raised sacrificial emitter core is then formed on the intrinsic base region followed by depositing a substantially conformal spacer layer over the sacrificial emitter core. Next, the spacer material is anisotropically etched such that a protective spacer ring is formed about the sacrificial emitter core. An extrinsic base is then formed by implanting dopant into the epitaxial base region wherein the sacrificial emitter core and the spacer ring preserve an emitter region. The spacer ring also serves to self-align the extrinsic base region to the emitter region. The protective sacrificial emitter core and spacer ring are then removed.