Kumar K Gala from 932 Hyer Ave, Orlando, FL 32803, age 46, Phone: 4078981175

Us Patents

Interprocessor Message Transmission Via Coherency-Based Interconnect
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US Patent:

7941499, May 10, 2011
Filed:

Mar 6, 2007
Appl. No.:

11/682867
Inventors:

Becky G. Bruce - Leander TX, US
Sanjay R. Deshpande - Austin TX, US
Michael D. Snyder - Austin TX, US
Gary L. Whisenhunt - Austin TX, US
Kumar Gala - Austin TX, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

G06F 15/167
US Classification:

709213, 709212, 709216, 711146
Abstract:

A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.

Distributed Processing System And Method
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US Patent:

8255919, Aug 28, 2012
Filed:

Jan 24, 2008
Appl. No.:

12/018872
Inventors:

Harlan T. Beverly - McDade TX, US
Kumar Gala - Austin TX, US
Charles A. Musta - Austin TX, US
Assignee:

Qualcomm Atheros, Inc. - San Jose CA
International Classification:

G06F 9/46
G06F 13/00
G06F 15/00
US Classification:

718105, 719328, 712 1
Abstract:

A method is disclosed that receives a function call at an application program interface. The method selects a first processor of a plurality of processors to execute the function call. The method further executes a first transmit function associated with a bus coupled to the first processor. The first transmit function includes a function parameter associated with the function call.

Processor With Hardware Thread Control Logic Indicating Disable Status When Instructions Accessing Shared Resources Are Completed For Safe Shared Resource Condition
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US Patent:

8615644, Dec 24, 2013
Filed:

Feb 19, 2010
Appl. No.:

12/708791
Inventors:

Becky Bruce - Leander TX, US
Giles R. Frazier - Austin TX, US
Bradly G. Frey - Austin TX, US
Kumar K. Gala - Austin TX, US
Cathy May - Ossining NY, US
Michael D. Snyder - Cedar Park TX, US
Gary Whisenhunt - Leander TX, US
James Xenidis - Carmel NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 9/38
US Classification:

712214, 712205, 712216
Abstract:

A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.

Method And System For Data Transfers Across Different Address Spaces
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US Patent:

20080183943, Jul 31, 2008
Filed:

Jan 31, 2007
Appl. No.:

11/669804
Inventors:

Becky G. Bruce - Leander TX, US
Michael D. Snyder - Austin TX, US
Gary L. Whisenhunt - Austin TX, US
Kumar Gala - Austin TX, US
Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX
International Classification:

G06F 12/02
US Classification:

711 1, 711E12002
Abstract:

A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.

Method And System For Communication Between Nodes
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US Patent:

20080239954, Oct 2, 2008
Filed:

Mar 21, 2008
Appl. No.:

12/053427
Inventors:

Harlan T. Beverly - McDade TX, US
Kumar Gala - Austin TX, US
Assignee:

BIGFOOT NETWORKS, INC. - Austin TX
International Classification:

G01R 31/08
US Classification:

370231
Abstract:

A method of communicating with a network interface includes providing a packet to the network interface, where the packet includes an address field indicating a destination of the packet. The network interface analyzes the address field, and determines if it reflects an address associated with the network interface. If not, the network interface provides the packet to a network. If the network interface determines the address field reflects an address associated with the interface, it provides information in the packet to an application executing at the network interface. Accordingly, information targeted to an application can be communicated by associating an address, such as a network address, with the network interface, allowing for communication of the information without extensive processing of each packet at the interface.

Virtualized Instruction Extensions For System Partitioning
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US Patent:

20130290585, Oct 31, 2013
Filed:

Apr 30, 2012
Appl. No.:

13/460287
Inventors:

Bryan D. Marietta - Cedar Park TX, US
Gary L. Whisenhunt - Leander TX, US
Kumar K. Gala - Austin TX, US
David B. Kramer - Cedar Park TX, US
International Classification:

G06F 13/24
G06F 13/14
US Classification:

710240, 710260
Abstract:

A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g., ) by executing a control instruction () to encode and store an access command (CMD) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register () at a physical address (PA) retrieved from a special purpose register () so that the partitioned device () can determine if the access command can be performed based on local access control information.

Virtualized Interrupt Delay Mechanism
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US Patent:

20130326102, Dec 5, 2013
Filed:

May 31, 2012
Appl. No.:

13/485120
Inventors:

Bryan D. Marietta - Cedar Park TX, US
Gary L. Whisenhunt - Leander TX, US
Kumar K. Gala - Austin TX, US
David B. Kramer - Cedar Park TX, US
International Classification:

G06F 13/24
US Classification:

710262, 710264
Abstract:

A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register () at a physical address (PA) retrieved from a special purpose register () so that the partitioned interrupt controller () can determine if the delay command can be performed based on local access control information.

Interrupt Priority Management Using Partition-Based Priority Blocking Processor Registers
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US Patent:

20140047149, Feb 13, 2014
Filed:

Aug 9, 2012
Appl. No.:

13/570843
Inventors:

Bryan D. Marietta - Cedar Park TX, US
Gary L. Whisenhunt - Leander TX, US
Kumar K. Gala - Austin TX, US
David B. Kramer - Cedar Park TX, US
International Classification:

G06F 13/26
US Classification:

710264
Abstract:

A method and circuit for a data processing system () provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers (-) located at the processor core () to enable quick and efficient interrupt priority blocking on a partition basis.