Kurt Gilbert Robinson

US Patent:

20020140690, Oct 3, 2002

Filed:

Mar 30, 2001

Appl. No.:

09/823831

Inventors:

Edward Gamsaragan - El Dorado Hills CA, US
Varghese George - Folsom CA, US
Peter Ruscito - Folsom CA, US
Kurt Robinson - Newcastle CA, US

International Classification:

G09G005/00

US Classification:

345/211000

Abstract:

A computer includes a computing display subsystem screen that includes a processor is detachably connected to the remainder of the computer. When the computing display subsystem is detached, communication may continue between the computing display subsystem and the base station using one of a plurality of techniques, including radio frequency or infrared communications.

US Patent:

20050246850, Nov 10, 2005

Filed:

Jul 30, 2003

Appl. No.:

10/524169

Inventors:

Kurt Robinson - Garden Grove CA, US

International Classification:

A47L013/20

US Classification:

015228000, 015247000, 015231000

Abstract:

During a televised entertainment event, a handheld cleaning device is used to wipe a stage or other planar surface to remove liquid there from. The device has an exterior displaying a visual advertisement, and the act of wiping the planar surface is televised, including the advertisement displayed on the device. This promotes over television the product or service in the advertisement.

US Patent:

52240703, Jun 29, 1993

Filed:

Dec 11, 1991

Appl. No.:

7/804965

Inventors:

Mickey L. Fandrich - Placerville CA
Virgil N. Kynett - El Dorado Hills CA
Kurt Robinson - Newcastle CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1140

US Classification:

365185

Abstract:

A circuit which monitors the internal state of flash memory array programming circuitry and conveys that state to circuitry external to the flash memory array so that external circuitry need not delay during any period in which a programming operation is taking place within the flash memory array.

US Patent:

59374233, Aug 10, 1999

Filed:

Dec 26, 1996

Appl. No.:

8/773168

Inventors:

Kurt B. Robinson - Newcastle CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1202

US Classification:

711103

Abstract:

A flash EEPROM memory device including a memory array having a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash storage device, and a register interface for receiving data and commands addressed to the blocks of flash EEPROM memory devices and generating signals for affecting the purpose of the commands in the device, the interface including a command register for receiving commands and a plurality of registers for providing the data stored in the query memory as output.

US Patent:

58227814, Oct 13, 1998

Filed:

Oct 30, 1992

Appl. No.:

7/969131

Inventors:

Steven Wells - Citrus Heights CA
Robert N. Hasbun - Shingle Springs CA
Kurt Robinson - Newcastle CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1204

US Classification:

711171

Abstract:

A solid state memory disk that stores data on a sector basis is described. The solid state disk includes an array of FLASH memory devices, which store the sectors of data. Each block of memory within the FLASH array includes data space for storing many sectors of data and a block sector translation table. The block sector translation table identifies each sector of data stored in the block's data space by a sector number. The solid state disk also includes a controller. Among its many responsibilities, the controller manages the writing of sector data into the array and the reading of sectors of data from the array. The controller responds to a write request by seeking an earlier version of the sector which has a logical sector number equal to the sector's sector number and marking that sector dirty. Afterward, the controller allocates free memory space for the sector of data. The sector of data is then written into the allocated memory space.

US Patent:

51596725, Oct 27, 1992

Filed:

Dec 28, 1989

Appl. No.:

7/458141

Inventors:

Joseph H. Salmon - Placerville CA
Robert E. Larsen - Shingle Springs CA
David A. Leak - Rancho Cordova CA
Kurt B. Robinson - Newcastle CA
Dhiraj Parmar - Diamond Springs CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1328

US Classification:

395325

Abstract:

Circuitry which when combined with an EPROM in a single integrated circuit for connection to a microprocessor which provides suitable signals utilized by the additional circuitry to provude faster access to the code or data stored in the EPROM than can be accomplished without such additional circuitry by providing zero wait state burst performance. A state machine is utilized to manage the interface between the microprocessor and the burst EPROM.

US Patent:

53882482, Feb 7, 1995

Filed:

Feb 16, 1994

Appl. No.:

8/198789

Inventors:

Kurt B. Robinson - Newcastle CA
Russell D. Eslick - Placerville CA
Markus A. Levy - Citrus Heights CA
David M. Brown - Fair Oaks CA
Lily C. Pao - Orangevale CA
Brian L. Dipert - Sacramento CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300
G11C 1606
G06K 19067

US Classification:

395425

Abstract:

A flash memory card is described which has a plurality of flash memories, each having a ready/busy output for indicating whether its respective one of the plurality of flash memories is busy or ready. A register circuit is provided for storing a plurality of mask data. A mode circuit is provided for choosing one of a first mode and a second mode, wherein a first mode signal is produced if the first mode is chosen and a second mode signal is produced if the second mode is chosen. A logic circuit is provided for performing logical operations with respect to the ready/busy output for each of the plurality of flash memories and the mask data in accordance with whether the first mode signal or the second mode signal is produced. If the first mode is chosen, the logic circuit produces a ready signal output for the flash memory card only if the ready/busy output of all the plurality of flash memories is ready. If the second mode is chosen, the logic circuit produces a ready signal output for the flash memory card each time any flash memory goes from being busy to being ready.

US Patent:

54285666, Jun 27, 1995

Filed:

Oct 27, 1993

Appl. No.:

8/144196

Inventors:

Kurt B. Robinson - Newcastle CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 506
G11C 1606

US Classification:

365 65

Abstract:

A memory card includes a plurality of nonvolatile memories, each having a pad for applying a busy signal indicating that a respective memory is busy and a circuit for coupling the busy signal to the pad. The pad of each memory is coupled to a node external to the memories. A resistive circuit is used for coupling a first voltage to the node. When each of the memories does not output the busy signal at the pad, the node assumes a first voltage. When the pad of at least one of the memories outputs the busy signal, the node assumes a ground voltage. An output pin is used for supplying a card busy output signal when at least one of the memories is indicated busy and an input pin is coupled to the node for receiving the card busy output signal at the node. A pass logic is coupled to the input and output pins for passing the card busy output signal directly from the input pin to the output pin. Each of the memories also includes an input pad for receiving a global power down control signal and a register for receive a software power down control signal.