Lan Thai Hoang

US Patent:

6373142, Apr 16, 2002

Filed:

Nov 15, 1999

Appl. No.:

09/440492

Inventors:

Lan H. Hoang - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2348

US Classification:

257783, 257795, 257787

Abstract:

The present invention provides a semiconductor chip package with a fillet which contains a high percentage of a filler material by weight and a method of assembly with a semiconductor chip package for adding filler material to a non-filled or low-filled underfill system. The method of assembly produces a chip package where the concentration of filler material within the underfill material between the chip and the package substrate may be varied from location to location within the underfill material. The filler material increases the mechanical rigidity of the underfill material after it has hardened. Thus, using the approach of the present invention, the percentage of filler material may be increased in regions of the underfill material where the mechanical stresses require a greater mechanical rigidity. The present invention may be applicable to increasing the reliability of chip packages where the chip and the package substrate are separated by a gap about 25-50 microns wide.

US Patent:

6475828, Nov 5, 2002

Filed:

Nov 10, 1999

Appl. No.:

09/437559

Inventors:

Lan Hoang - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2148

US Classification:

438108, 438613, 22818022

Abstract:

A method is disclosed for applying underfill to a flip-chip package comprising integrated circuit die and a substrate. First, a first non-filled no flow flux-underfill is applied to a plurality of solder bumps disposed on an active surface of the integrated circuit die. Next, the integrated circuit die is placed on the substrate such that the solder bumps align with corresponding bond pads on the substrate, thereby creating an assembly. A second filler-loaded no flow flux-underfill is then dispensed on a side of the substrate such that the second filler-loaded no flow flux-underfill flows by capillary action between the die and substrate to fill a gap therebetween. Finally, the assembly is passed through a furnace such that both the first non-filled no flow flux-underfill and the second filled no flow flux-underfill are cured, and such that the solder bumps are reflowed.

US Patent:

6744131, Jun 1, 2004

Filed:

Apr 22, 2003

Appl. No.:

10/421486

Inventors:

Lan Hoang Hoang - Fremont CA
Hoa Lap Do - Herald CA
Leilei Zhang - Sunnyvale CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 2312

US Classification:

257704, 257778, 257723, 257724, 257786, 257693, 257678

Abstract:

An IC package provides structural rigidity to a flexible substrate, but still allows access to mounted capacitors after package assembly. In a flip chip package, the IC die is mounted face down on a flexible laminate substrate. A metal lid is mounted above and in contact with the die. The metal lid includes openings over portions of an outer region of the substrate to accommodate the capacitors. However, portions of the metal lid extend to the corners of the substrate to provide structural rigidity to the flexible substrate. Some embodiments are directed to packages configured as described above, but in which an IC die has yet to be mounted.

US Patent:

7061102, Jun 13, 2006

Filed:

Jun 11, 2001

Appl. No.:

09/879875

Inventors:

Abu K. Eghan - San Jose CA, US
Lan H. Hoang - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 23/34
H01L 22/04

US Classification:

257713, 257724, 257730

Abstract:

A semiconductor flipchip package includes a central cavity area on the first major side for receiving a flipchip die therein. The package substrate is substantially made from a single material that serves as the support and stiffener and provides within the cavity floor all the connecting points for flipchip interconnection to the silicon die. The integral cavity wall serves as a stiffener member of the package and provides the required mechanical stability of the whole arrangement without the need for a separate stiffener material to be adhesively attached. The cavity walls may contain extra routing metallization to create bypass capacitors to enhance electrical performance. Optional methods to cover the silicon die enhance thermal performance of the package.

US Patent:

7098542, Aug 29, 2006

Filed:

Nov 7, 2003

Appl. No.:

10/703327

Inventors:

Lan H. Hoang - Fremont CA, US
Paul Ying-Fung Wu - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 23/48
H01L 23/02

US Classification:

257778, 257686

Abstract:

A semiconductor structure includes a carrier having a cavity formed in a top portion thereof, and a plurality of conductive contacts formed on a top surface of the carrier and positioned around the periphery of the cavity. A number of first coplanar dice are back-side mounted to a top surface of the cavity, and a number of second coplanar dice are flip-chip mounted to the first dice, wherein each of the first dice is electrically connected to two corresponding adjacent second dice to connect the dice in a cascade configuration. For some embodiments, selected dice are flip-chip mounted to the carrier. For other embodiments, selected dice are wire-bond connected to the carrier.

US Patent:

7378733, May 27, 2008

Filed:

Aug 29, 2006

Appl. No.:

11/511969

Inventors:

Lan H. Hoang - Fremont CA, US
Paul Ying-Fung Wu - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 23/34

US Classification:

257724, 257778, 257E23178

Abstract:

Composite flip-chip with encased components and method of fabricating the same is described. One aspect of the invention relates to fabricating composite flip-chip packages for integrated circuit dice. Interposing substrates are formed. At least one discrete component is attached to a bottom surface of each of the interposing substrates. A first array of solder balls is placed on the bottom surface of each of the interposing substrates. The interposing substrates are mounted to a carrier strip. The integrated circuit dice are attached to top surfaces of the interposing substrates. The integrated circuit dice and the interposing substrates are encapsulated in molding compound to define flip-chip assemblies.

US Patent:

7696006, Apr 13, 2010

Filed:

Apr 4, 2008

Appl. No.:

12/098053

Inventors:

Lan H. Hoang - Fremont CA, US
Paul Ying-Fung Wu - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 21/44
H01L 21/48
H01L 21/50

US Classification:

438107, 438108, 257E21503

Abstract:

Composite flip-chip with encased components and method of fabricating the same is described. One aspect of the invention relates to fabricating composite flip-chip packages for integrated circuit dice. Interposing substrates are formed. At least one discrete component is attached to a bottom surface of each of the interposing substrates. A first array of solder balls is placed on the bottom surface of each of the interposing substrates. The interposing substrates are mounted to a carrier strip. The integrated circuit dice are attached to top surfaces of the interposing substrates. The integrated circuit dice and the interposing substrates are encapsulated in molding compound to define flip-chip assemblies.

US Patent:

7906857, Mar 15, 2011

Filed:

Mar 13, 2008

Appl. No.:

12/047676

Inventors:

Lan H. Hoang - San Jose CA, US
Raghunandan Chaware - Sunnyvale CA, US
Laurene Yip - San Francisco CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 23/48

US Classification:

257783, 257675, 257706, 257778, 257782, 257E33075, 257E23051, 257E21511, 257E21514, 438106, 438108, 438118, 438119, 438122

Abstract:

A molded integrated circuit package is described. The molded integrated circuit package comprises a substrate having a plurality of contacts on a first surface; a die having a plurality of solder bumps on a first surface, the plurality of solder bumps being coupled to the plurality of contacts on the first surface of the substrate; an adhesive material positioned on a second surface of the die; a lid attached to the adhesive material; and an encapsulant positioned between the lid and the substrate. Methods of forming molded integrated circuit packages are also disclosed.