Lan Y Lin

US Patent:

20060018170, Jan 26, 2006

Filed:

Jan 21, 2005

Appl. No.:

11/040895

Inventors:

Mario Au - Fremont CA, US
Jason Mo - Fremont CA, US
Ta-Chung Ma - San Jose CA, US
Lan Lin - Palo Alto CA, US

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

365205000

Abstract:

A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells, a third sense amplifier circuit and a fourth sense amplifier circuit. Each of the sense amplifier circuits is independently controlled. Each queue of the multi-queue system has entries in both the first and second memory blocks. A first queue is accessed by alternately accessing the first and second arrays via the first and third sense amplifier circuits. A second queue is subsequently accessed by alternately accessing the first and second arrays via the second and fourth sense amplifier circuits.