Lance Gregory Hehenberger

US Patent:

8140925, Mar 20, 2012

Filed:

Jun 26, 2007

Appl. No.:

11/768791

Inventors:

Ralph E. Bellofatto - Ridgefield CT, US
Matthew R. Ellavsky - Rochester MN, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Thomas M. Gooding - Rochester MN, US
Rudolf A. Haring - Cortlandt Manor NY, US
Lance G. Hehenberger - Leander TX, US
Martin Ohmacht - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G06F 1/12

US Classification:

714731, 713400

Abstract:

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

US Patent:

20060222004, Oct 5, 2006

Filed:

Apr 1, 2005

Appl. No.:

11/097735

Inventors:

Bruce Beukema - Hayfield MN, US
Lance Hehenberger - Byron MN, US
Nathaniel Sellin - Rochester MN, US
Robert Shearer - Rochester MN, US
Bruce Walk - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/28

US Classification:

370466000, 370392000

Abstract:

In a first aspect, a first method is provided for transferring data using an Infiniband (IB) protocol. The first method includes the steps of (1) receiving a non-IB packet having header data and payload data at a first node of a computer system; and (2) modifying data in the non-IB packet to convert the non-IB packet to an IB packet having header data and payload data. The header data of the non-IB packet is not included in the payload data of the IB packet resulting from the conversion. Numerous other aspects are provided.

US Patent:

20080317249, Dec 25, 2008

Filed:

Jun 23, 2008

Appl. No.:

12/144319

Inventors:

Matthew D. Bates - Austin TX, US
Lance G. Hehenberger - Leander TX, US

International Classification:

H04L 9/00

US Classification:

380255

Abstract:

A system for encrypting and decrypting data is provided. The system includes a client for receiving a data packet, setting a value of a crypto bit, and transmitting the data packet over a system bus. A crypto module receives the data packet from the system bus and performs a cryptology function on the data packet based on a first value of the crypto bit. A memory controller receives the data packet from the system bus and performs non-cryptology functions on the data packet based on a second value of the crypto bit.

US Patent:

20200225952, Jul 16, 2020

Filed:

Mar 26, 2020

Appl. No.:

16/831055

Inventors:

- Armonk NY, US
Kevin Barnett - Austin TX, US
Debapriya Chatterjee - Austin TX, US
Bryant Cockcroft - Austin TX, US
Jamory Hawkins - Austin TX, US
Lance G. Hehenberger - Cedar Park TX, US
Jeffrey Kellington - Pflugerville TX, US
Paul Lecocq - Round Rock TX, US
Lawrence Leitner - Austin TX, US
John A. Schumann - Austin TX, US
Paul K. Umbarger - Austin TX, US
Karen Yokum - Austin TX, US

International Classification:

G06F 9/30
G06F 11/07
G06F 9/38
G06F 11/00

Abstract:

A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

US Patent:

20200201778, Jun 25, 2020

Filed:

Dec 20, 2018

Appl. No.:

16/227381

Inventors:

- Armonk NY, US
David Campbell - Austin TX, US
Lance Hehenberger - Cedar Park TX, US
Madhusudan Kadiyala - Bangalore, IN

International Classification:

G06F 12/1009
G06F 12/0891
G06F 9/30
G06F 9/48
G06F 9/38
G06F 9/345
G06F 12/0862

Abstract:

Verification of asynchronous page fault in a simulated environment. The methods include providing a simulated environment that includes a simulated processor core, a memory, and an interrupt handler. The methods also include executing a test code in the simulated environment by: executing a non-irritator thread code comprising a plurality of load instructions that span at least two slices of the simulated processor core, executing a first irritator thread code to bias against the execution of the plurality of load instruction by one of the at least two slices of the simulated processor core, and executing a second irritator thread code to invalidate caching of page table entries during execution of the plurality of load instructions in a fast access cache memory.