Lance Jack Shelton

US Patent:

7818525, Oct 19, 2010

Filed:

Sep 24, 2009

Appl. No.:

12/566421

Inventors:

Holloway H. Frost - Houston TX, US
Charles J. Camp - Sugar Land TX, US
Timothy J. Fisher - Cypress TX, US
James A. Fuxa - Houston TX, US
Lance W. Shelton - Houston TX, US

Assignee:

Texas Memory Systems, Inc. - Houston TX

International Classification:

G06F 12/00

US Classification:

711165, 711103, 711E12001, 36518525

Abstract:

Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.

US Patent:

8190842, May 29, 2012

Filed:

Sep 10, 2010

Appl. No.:

12/879966

Inventors:

Holloway H. Frost - Houston TX, US
Charles J. Camp - Sugar Land TX, US
Timothy J. Fisher - Cypress TX, US
James A. Fuxa - Houston TX, US
Lance W. Shelton - Houston TX, US

Assignee:

Texas Memory Systems, Inc. - Houston TX

International Classification:

G06F 12/00

US Classification:

711165, 711103, 711E12001, 711170, 36518525

Abstract:

Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.

US Patent:

8495423, Jul 23, 2013

Filed:

Dec 30, 2010

Appl. No.:

12/982702

Inventors:

Holloway H. Frost - Houston TX, US
Don D. Davis - Katy TX, US
Adrian P. Glover - Houston TX, US
Lance W. Shelton - Houston TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 24, 714 22

Abstract:

A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.

US Patent:

20110040927, Feb 17, 2011

Filed:

Dec 21, 2009

Appl. No.:

12/643688

Inventors:

James A. Fuxa - Houston TX, US
Lance W. Shelton - Houston TX, US
Justin C. Haggard - Houston TX, US

Assignee:

TEXAS MEMORY SYSTEMS, INC. - Houston TX

International Classification:

G06F 12/02

US Classification:

711103, 711E12008

Abstract:

Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.

US Patent:

20120233391, Sep 13, 2012

Filed:

May 28, 2012

Appl. No.:

13/481930

Inventors:

Holloway H. Frost - Houston TX, US
Charles J. Camp - Sugar Land TX, US
Timothy J. Fisher - Cypress TX, US
James A. Fuxa - Houston TX, US
Lance W. Shelton - Houston TX, US

Assignee:

TEXAS MEMORY SYSTEMS, INC. - Houston TX

International Classification:

G06F 12/02

US Classification:

711103, 711E12008

Abstract:

Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.

US Patent:

20130124788, May 16, 2013

Filed:

Dec 6, 2012

Appl. No.:

13/707387

Inventors:

Holloway H. FROST - Houston TX, US
Charles J. CAMP - Sugar Land TX, US
Ken SCIANNA - Houston TX, US
Lance W. SHELTON - Houston TX, US

Assignee:

TEXAS MEMORY SYSTEMS, INC. - Houston TX

International Classification:

G06F 12/02

US Classification:

711103

Abstract:

The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a FLASH memory system. The methods and apparatuses involve a system controller for a plurality of FLASH memory devices in the FLASH memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes.

US Patent:

20130294163, Nov 7, 2013

Filed:

Jul 2, 2013

Appl. No.:

13/934217

Inventors:

Don D. DAVIS - Katy TX, US
Adrian P. GLOVER - Houston TX, US
Lance W. SHELTON - Houston TX, US

International Classification:

G11C 16/06

US Classification:

36518511, 36518518

Abstract:

A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.

US Patent:

20160283327, Sep 29, 2016

Filed:

Jun 6, 2016

Appl. No.:

15/175003

Inventors:

- Armonk NY, US
Don D. DAVIS - Katy TX, US
Adrian P. GLOVER - Houston TX, US
Lance W. SHELTON - Houston TX, US

International Classification:

G06F 11/14
G06F 3/06
G06F 11/20
G06F 1/28
G06F 1/30
G06F 13/40
G06F 12/10

Abstract:

A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.