Lane K Smith

US Patent:

7599461, Oct 6, 2009

Filed:

Sep 29, 2006

Appl. No.:

11/541498

Inventors:

Pervez M. Aziz - Dallas TX, US
Vladimir Sindalovsky - Perkasie PA, US
Lane A. Smith - Easton PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03D 3/24

US Classification:

375373, 375229, 375230, 375231, 375232, 375233, 375371

Abstract:

Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist pattern. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. One or more of said phase updates are modified by the present invention if said DFE detected data satisfies one or more predefined conditions. A number of mechanisms are disclosed for qualifying or modifying the DFE phase detector updates based on the detected data pattern.

US Patent:

7616686, Nov 10, 2009

Filed:

Feb 17, 2006

Appl. No.:

11/356691

Inventors:

Pervez M. Aziz - Dallas TX, US
Gregory W. Sheets - Bangor PA, US
Lane A. Smith - Easton PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03H 7/30

US Classification:

375233

Abstract:

Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.

US Patent:

7706487, Apr 27, 2010

Filed:

Oct 12, 2004

Appl. No.:

10/964056

Inventors:

Pervez Mirza Aziz - Dallas TX, US
Donald Raymond Laturell - Allentown PA, US
Mohammad Shafiul Mobin - Orefield PA, US
Gregory W. Sheets - Bangor PA, US
Lane A. Smith - Easton PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04B 1/10

US Classification:

375350

Abstract:

In training a SERDES, a Common Electrical Interface (CEI) training frame, having certain bits of information embedded therein, is transmitted over a path which comprises transmitter, channel, and receiver components. The present invention analyzes the resulting received signal and determines the effective aggregate channel impulse response of these three components. The invention then determines an estimate of the inverse of this aggregate channel and uses this determination to reduce distortions that have been introduced into a signal that has been transmitted over the path.

US Patent:

8040984, Oct 18, 2011

Filed:

Dec 31, 2007

Appl. No.:

11/967602

Inventors:

Pervez M. Aziz - Dallas TX, US
Adam B. Healey - Newburyport MA, US
Mohammad S. Mobin - Orefield PA, US
Gary E. Schiessler - Allentown PA, US
Gregory W. Sheets - Breinigsville PA, US
Lane A. Smith - Easton PA, US
Paul H. Tracy - Lehigh PA, US
Geoffrey Zhang - Allentown PA, US

Assignee:

Agere System Inc. - Allentown PA

International Classification:

H04L 25/08
H04L 7/10
H04L 7/00

US Classification:

375346, 375345, 375371

Abstract:

Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i. e. , rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.

US Patent:

8107522, Jan 31, 2012

Filed:

Oct 11, 2007

Appl. No.:

11/870908

Inventors:

Pervez M. Aziz - Dallas TX, US
Mohammad S. Mobin - Orefield PA, US
Lane A. Smith - Easton PA, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H03H 7/30

US Classification:

375233, 375229, 375230, 375231, 375232, 375234, 375316, 375317, 375340, 375344, 375345, 375346, 375350, 708300

Abstract:

Methods and apparatus are provided for determining receiver filter coefficients for a plurality of phases. One or more coefficients for a receiver filter are determined by determining a first coefficient for a first phase of a data eye; and determining a second coefficient for a second phase of the data eye. The receiver filter may be, for example, a decision-feedback equalizer. The first and second coefficients may be determined by performing an LMS adaptation of decision-feedback equalization coefficients. In another embodiment, the first and second coefficients may be determined by obtaining eye opening metrics from a data eye monitor corresponding to each of the respective first phase and the second phase; and determining the respective first and second coefficients based on the eye opening metrics. The first and second phases can correspond to odd and even phases.

US Patent:

8315298, Nov 20, 2012

Filed:

Oct 31, 2007

Appl. No.:

11/930780

Inventors:

Pervez M Aziz - Dallas TX, US
Mohammad S Mobin - Orefield PA, US
Gregory W Sheets - Breinigsville PA, US
Lane A Smith - Easton PA, US
Paul H. Tracy - Schnecksville PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03H 7/30

US Classification:

375232

Abstract:

Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).

US Patent:

8432959, Apr 30, 2013

Filed:

Oct 31, 2007

Appl. No.:

11/930814

Inventors:

Pervez M. Aziz - Dallas TX, US
Mohammad S. Mobin - Orefield PA, US
Gregory W Sheets - Breinigsville PA, US
Lane A. Smith - Easton PA, US
Paul H. Tracy - Schnecksville PA, US

Assignee:

Agere Systems LLC - Allentown PA

International Classification:

H03H 7/30
H03K 5/159

US Classification:

375232, 375230, 375231

Abstract:

Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step.