Lanzhong L Wang

US Patent:

6564354, May 13, 2003

Filed:

Jun 1, 2000

Appl. No.:

09/586167

Inventors:

Lanzhong Wang - Ft Collins CO
Paul Donald Hylander - Plano TX

Assignee:

Hewlett Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1750

US Classification:

716 3, 716 1

Abstract:

A methodology for translating conditional expressions of a non-Verilog hardware description language (HDL) program, not readily recognized by Verilog HDL, which can then be used to prove out a logic circuit design. IF/CASE/COND (ICC) expressions occurring within the HDL program that are not recognized by Verilog HDL are categorized and accordingly translated to IF/CASE statements in Verilog HDL syntax. For ICC expressions that are part of a conditional or binary operator expression, a globally incremental variable that is representative of a corresponding variable of an ICC expression is created for each variable of the ICC expression. The ICC expression is then assigned to the globally incremental variable(s) which is placed in an always statement that is recognized by Verilog HDL. Synthesis can then be performed on the always statement by a processor to generate a logic circuit representative of the module of the non-Verilog HDL program. Translation of other conditional expressions in the non-Verilog HDL program, including simple ICC expressions, nested ICC expressions, special expressions, and edge-triggered statements, can additionally be performed.

US Patent:

6625798, Sep 23, 2003

Filed:

Jul 25, 2000

Appl. No.:

09/624790

Inventors:

Richard A. Ferreri - Ft. Collins CO
Lanzhong Wang - Ft Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1750

US Classification:

716 18, 716 1, 716 3, 717141, 717159

Abstract:

A methodology for translating multiple bit conditional expressions of a non-Verilog hardware description language (HDL) program, not readily recognized by Verilog HDL, which can then be used to realize a logic circuit design embodied by the non-Verilog HDL program. Conditional IF expressions occurring within the HDL program that are not recognized by Verilog HDL are processed so that they can be accordingly translated to Verilog HDL syntax. If the conditional IF expression is a multiple-bit expression, a binary operator statement having bit-wise binary operators, including two AND operators, one OR operator, and one NOT operator, that is equivalent to the conditional IF expression is created. If either the THEN expr and/or the ELSE expr expressions are themselves multiple-bit expressions nested within the main multi-bit IF expression, then the nested multiple-bit expressions expr and/or expr in the binary operator statement must be replaced by the appropriate incremental variable(s) to create an always statement that can be translated to generate a Verilog HDL statement that is equivalent to the conditional expression. The nested multiple-bit expressions expr and/or expr are represented within the always statement by one or more corresponding incremental variables.

US Patent:

6801884, Oct 5, 2004

Filed:

Feb 9, 2001

Appl. No.:

09/779965

Inventors:

Richard Anthony Ferreri - Ft. Collins CO
Lanzhong Wang - Ft Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1750

US Classification:

703 13, 703 17

Abstract:

The present invention allows traversal of net occurrences of a light weight occurrence model. In traversing down, a port iterator is preferably used, while in traversing up a port instance iterator is preferably used. The selected iterator is initialized with information about the current occurrence net from the inventive occurrence node that describes the occurrence nets owner and folded model describer. In traversing up, the iterator finds the next port that connects to the folded model net indicated by the describer used during initialization. Then, using information stored in the model, the iterator finds the occurrence net object that is one level higher in hierarchy than the original occurrence net object. In traversing down, the iterator finds the next port instance that connects to the folded model net indicated by the describer used during initialization. Then, using information stored in the model, the iterator finds the occurrence net object that is one level lower in hierarchy than the original occurrence net object.

US Patent:

6823300, Nov 23, 2004

Filed:

Nov 10, 2000

Appl. No.:

09/709695

Inventors:

Richard Anthony Ferreri - Ft. Collins CO
Lanzhong Wang - Ft Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1750

US Classification:

703 15, 703 14, 703 16

Abstract:

The inventive lightweight occurrence model uses a folded connectivity model which includes occurrence nodes. Each occurrence node includes occurrence specific data or a pointer to such data, a pointer to a parent occurrence node, and a pointer to a folded model describer. Thus, the information that would present in a full occurrence model can be included in the inventive lightweight occurrence model. The inventive model does not maintain duplicate information and requires less memory to store the inventive model. Since the inventive occurrence model is smaller than the full occurrence model, complex circuit designs, e. g. microprocessors, can be represented by the inventive lightweight occurrence model. Thus, low level characteristics of the design, e. g. , timing delays, can be examined.

US Patent:

20050060314, Mar 17, 2005

Filed:

Apr 22, 2004

Appl. No.:

10/829488

Inventors:

Lanzhong Wang - Fort Collins CO, US
Richard Ferreri - Fort Collins CO, US
John Applin - Fort Collins CO, US

International Classification:

G06F007/00

US Classification:

707007000

Abstract:

One embodiment of the invention involves a data structure that is stored on a computer-readable medium comprising a sorted portion that contains a plurality of entries that are sorted into an order, an unsorted portion that contains a plurality of entries that have not been sorted, and a boundary that separates the sorted portion and the unsorted portion. The sorted portion of the data structure may be searched with O(logN) performance while an entry is added to the unsorted portion.

US Patent:

61190799, Sep 12, 2000

Filed:

Apr 24, 1997

Appl. No.:

8/842460

Inventors:

Lanzhong Wang - Fort Collins CO
Charles W. Cairns - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1727
G06F 1728

US Classification:

704 8

Abstract:

Methods and structure for storing log messages in a tokenized, international format and for presenting (viewing, printing, etc) the tokenized log message in a locally preferred native language. Log messages from a computing system or application are stored in an international tokenized format which remains constant regardless of the particular nation in which the system or application is operated. The tokenized format includes a message ID field which identifies a unique message and includes parameters values which are to replace variable portions, if any, of the identified message. A plurality of localized message catalog files are available to retrieve a localized native language string which corresponds to each tokenized message. The message ID field serves as an index to the localized catalog files. A viewer program then retrieves a localized text string message from a selected message catalog file replacing any variable portions identified therein with parameter values supplied in the tokenized message.