Larry Steven Latham

US Patent:

51810956, Jan 19, 1993

Filed:

Apr 19, 1991

Appl. No.:

7/688196

Inventors:

Dan M. Mosher - Plano TX
Larry Latham - Garland TX
Bob Todd - Plano TX
Cornelia H. Blanton - Plano TX
Joe R. Trogolo - Plano TX
David R. Cotton - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2702
H01L 2704
H01L 2910

US Classification:

257370

Abstract:

An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.

US Patent:

50343378, Jul 23, 1991

Filed:

Aug 29, 1990

Appl. No.:

7/576136

Inventors:

Dan M. Mosher - Plano TX
Cornelia H. Blanton - Plano TX
Joe R. Trogolo - Plano TX
Larry Latham - Garland TX
David R. Cotton - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21331
H01L 2174
H01L 2176

US Classification:

437 31

Abstract:

A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.

US Patent:

52565823, Oct 26, 1993

Filed:

Nov 27, 1991

Appl. No.:

7/800869

Inventors:

Dan M. Mosher - Plano TX
Cornelia H. Blanton - Plano TX
Joe R. Trogolo - Plano TX
Larry Latham - Garland TX
David R. Cotton - Plano TX
Bob Todd - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2100
H01L 2102
H01L 2122
H01L 2126

US Classification:

437 31

Abstract:

The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known. For example, the present integrated circuit chip, uses bipolar power transistors instead of vertical DMOS power transistors for power applications.

US Patent:

51536978, Oct 6, 1992

Filed:

May 6, 1991

Appl. No.:

7/695821

Inventors:

Dan M. Mosher - Plano TX
Cornelia H. Blanton - Plano TX
Joe R. Trogolo - Plano TX
Larry Latham - Garland TX
David R. Cotton - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2702

US Classification:

357 43

Abstract:

An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.