Larry G Paulson

US Patent:

41036786, Aug 1, 1978

Filed:

Apr 21, 1977

Appl. No.:

5/789713

Inventors:

Ismet Karacan - Houston TX
Larry G. Paulson - Minneapolis MN
Gerald W. Timm - Minneapolis MN

Assignee:

American Medical Systems, Inc. - Minneapolis MN

International Classification:

A61B 500
G01D 1510

US Classification:

128 205V

Abstract:

Apparatus for generating and recording signals from two separate sensors on a patient adapted to provide an indication of the condition of an anatomical member to be monitored. A control cabinet having an integral strip chart recorder is provided with plug in inputs for two externally connected strain gauges. Each strain gauge makes up one leg of a bridge circuit. The bridge outputs are amplified and multiplexed into a single channel strip chart recorder having a single, heated stylus which records two separate traces based on the signals received from the two sensors. Heat to the recordinng pen or stylus is turned off during switching excursions of the pen between the two traces so as to eliminate shading and marking which would otherwise occur on the recording chart between the traces at slow chart speeds. In the nocturnal penile tumescence monitoring application for which the apparaus is primarily intended, two mercury strain gauges in the form of elastomer rings are positioned at the base and tip of the penis. Minute variations in penile size occurring during the Rapid Eye Movement stages of sleep are sensed by the strain gauges, amplified, through bridge circuits and recorded in two separate traces.

US Patent:

45518505, Nov 5, 1985

Filed:

Feb 7, 1983

Appl. No.:

6/464624

Inventors:

Larry J. Werth - Eagan MN
Larry G. Paulson - Moundsview MN

Assignee:

Pattern Processing Technologies, Inc. - Minneapolis MN

International Classification:

G06K 970

US Classification:

382 18

Abstract:

A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides an address stream containing a plurality of interleaved sequences of addresses to the image buffer and to a read/write response memory. The next address of each sequence provided by the address sequencer is based upon the current address of that sequence and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats an address in a sequence, that address sequence is in a repetitive address loop as long as the image stored in the image buffer remains constant. During a training mode, a pattern to be recognized is supplied to the image buffer and a training code representing a desired response is written into the response memory at selected locations that correspond to addresses in the address loop being generated. During a later recognition mode, when the same pattern is supplied to the image buffer, the same address loop is again generated.

US Patent:

45504318, Oct 29, 1985

Filed:

Feb 7, 1983

Appl. No.:

6/464588

Inventors:

Larry J. Werth - Eagan MN
Larry G. Paulson - Moundsview MN

Assignee:

Pattern Processing Technologies, Inc. - Minneapolis MN

International Classification:

G06K 900

US Classification:

382 1

Abstract:

An address sequencer produces an address stream which includes a plurality of interleaved sequences of addresses. Each sequence is a function of input data which is received when an input pattern is sampled by that sequence, so that a repetitive address loop is generated which characterizes the pattern. The address sequencer includes a shift register with a programmable feedback circuit which provides a feedback bit to the first stage of the shift register based upon bits from selected stages of the shift register. During each operating cycle of the address sequencer, a counter provides a sequence identification number which identifies a particular sequence. A stored address selected by the sequence identification number is provided as the present address for that sequence (and the output of the address sequencer). In addition, the shift register is loaded with a multibit word derived from that stored address. The shift register is then shifted a predetermined number of times, and the feedback bit is derived from stages of the shift register which are selected based upon the sequence identification number.

US Patent:

45049700, Mar 12, 1985

Filed:

Feb 7, 1983

Appl. No.:

6/464350

Inventors:

Larry J. Werth - Eagan MN
Larry G. Paulson - Moundsview MN

Assignee:

Pattern Processing Technologies, Inc. - Minneapolis MN

International Classification:

G06K 970

US Classification:

382 14

Abstract:

A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides an address stream containing a plurality of interleaved sequences of addresses to the image buffer and to a read/write response memory. The next address of each sequence provided by the address sequencer is based upon the current address of that sequence and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats an address in a sequence, that address sequence is in a repetitive address loop as long as the image stored in the image buffer remains constant. The address loop continues to be generated, since the address sequencer always produces the same next address for that sequence based upon the same current address and the same sample value stored at that current address. During a training mode, a pattern to be recognized is supplied to the image buffer and a training code representing a desired response is written into the response memory at selected locations that correspond to addresses in the address loop being generated.