Larry W Petersen

US Patent:

7373266, May 13, 2008

Filed:

Jul 28, 2006

Appl. No.:

11/460951

Inventors:

Larry Petersen - Pocatello ID, US
Jose Taveira - Pocatello ID, US

Assignee:

ON Semiconductor - Phoenix AZ

International Classification:

G06F 19/00

US Classification:

702104, 73708, 374 1, 702 50, 702 85, 702 86, 702 99

Abstract:

Calibration of a sensor circuit that includes a sensor, a temperature measurement circuit and a signal processing path. The sensor senses a physical parameter to be measured and generates an electrical sensor output signal representing the physical parameter. The temperature measurement circuit outputs a measured temperature. The signal processing path is coupled to the sensor so as to receive the electrical sensor output signal and use the measured temperature to compensate for temperature variations in the electrical sensor output signal. During calibration, the output voltage of the signal processing path is measured at multiple temperatures, and at multiple values of the physical parameter being measured at each temperature while the signal processing path is disconnected from using the measured temperature of the temperature measurement circuit.

US Patent:

8081006, Dec 20, 2011

Filed:

Jul 28, 2006

Appl. No.:

11/460948

Inventors:

Munenori Tsuchiya - Ueda, JP
Lucas Laren Piquet - Pocatello ID, US
Larry Petersen - Pocatello ID, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

G01R 27/08

US Classification:

324721

Abstract:

A sensor temperature compensation circuit that includes a sensor and non-linear temperature compensation circuit that compensates for non-linear temperature dependencies in offset and/or gain generated by the sensor. For instance, to at least partially compensate for offset temperature dependencies, a summer adds two offset compensation signals, the ratio of the second to the first being a function of temperature. The summed signal may then be multiplied by a function of temperature. The summed signal may then be used to provide the non-linear temperature compensation to the offset. Alternatively or in addition, to at least partially compensate for gain temperature dependencies, a summer adds two gain compensation signals, the ratio of the second to the first being a function of temperature. The summed signal may then be multiplied by a function of temperature. The summed signal may then be used to provide non-linear temperature compensation to the gain.

US Patent:

58380469, Nov 17, 1998

Filed:

Jun 13, 1996

Appl. No.:

8/665136

Inventors:

Rustom F. Irani - Santa Clara CA
Boaz Eitan - Ra'anana, IL
Mark Michael Nelson - Pocatello ID
Larry Willis Petersen - Pocatello ID

Assignee:

Waferscale Integration Inc. - Fremont CA
American Microsystems, Inc. - Pocatello ID

International Classification:

H01L 2976

US Classification:

257369

Abstract:

A read only memory (ROM) array is disclosed which includes a) a voltage supply providing an operating voltage level, b) a plurality of word-lines, c) a multiplicity of ROM transistors, and d) a word-line clamper. The ROM transistors are divided into turned on and turned off transistors. Each ROM transistor has a gate connected to one of the word-lines, a gate oxide beneath the gate, whose thickness is less than 250. ANG. , and a channel beneath the gate oxide. The turned off transistors additionally have a ROM implant in their channel whose dosage is no larger than the amount which generates a predetermined desired minimal band-to-band tunneling current The ROM implant and gate oxide thickness define a threshold voltage for the tamed off tranistors, the threshold voltage being less than the operating voltage level. The word-line damper provides a word-line voltage to each of the word-lines, the word-line voltage being clamped to a voltage level no higher than the threshold voltage of the turned off transistor.

US Patent:

58381686, Nov 17, 1998

Filed:

Sep 5, 1996

Appl. No.:

8/708595

Inventors:

Larry W. Petersen - Pocatello ID

Assignee:

American Microsystems, Inc. - Pocatello ID

International Classification:

H03K 19092

US Classification:

326 81

Abstract:

An input buffer capable of operating at a first power supply voltage level or a second power supply voltage level with the operating voltage level selectable during manufacture. At least one shortable transistor is disposed between the power supply voltage input and a buffer circuit which is connected between an input and an output of the buffer circuit. When the first voltage is the intended operating voltage the at least one shortable transistor is shorted. The first operating voltage level meets the requirements of a CMOS device and the second operating voltage level meets the requirements of a TTL device. The shortable transistor can be either a p-channel or an n-channel transistor and the short can be done by a metal layer short, a polysilicon short, a depletion implant, or with vias during manufacture. Transistors in the buffer circuit are sized to provide an acceptable TTL device level trip point when the input buffer is operated at 5 volts and which also provides an acceptable CMOS device level trip point when the input buffer is operated at 3 volts. Transistors in the buffer circuit are provided to turn OFF the input buffer at the direction of an external circuit.

US Patent:

56823533, Oct 28, 1997

Filed:

Jun 13, 1996

Appl. No.:

8/665151

Inventors:

Boaz Eitan - Ra'anana, IL
Larry Willis Petersen - Pocatello ID
Yaron Slezak - Kiriat Motzkin, IL

Assignee:

Waferscale Integration Inc. - Fremont CA
American Microsystems, Inc. - Pocatello ID

International Classification:

G11C 800

US Classification:

365233

Abstract:

A clock delay circuit for generating a delay for a sense amplifier release signal in an integrated circuit semiconductor memory device is disclosed. Rather than utilize traditional programmable capacitors that must be trimmed on a die by die basis, the novel clock delay circuit disclosed utilizes a small ROM, EPROM, EEPROM or FLASH array coupled to a bit line emulator to provide a clock delay matched to the larger main array. The size of the small memory array is on the order of 5 to 10 bit lines by 5 to 10 word lines. One cell within the small array is fixed to be continuously selected. The selected cell is coupled to the clock delay node along with the bit line emulator. The bit line emulator models the capacitance of the actual bit line used in the main array. However, the circuit is constructed so that a much larger signal is generated by the delay circuit such that sense amplifiers detect the correct signal. The CMOS based clock delay circuit uses the emulated array to generate a delta or margin that accurately tracks the delays within the main array with variations in temperature, supply voltage and process.