Laura E Fick

US Patent:

20190258695, Aug 22, 2019

Filed:

May 2, 2019

Appl. No.:

16/402090

Inventors:

- Austin TX, US
Michael Henry - Austin TX, US
Laura Fick - Austin TX, US
Malav Parikh - Austin TX, US
Skylar Skrzyniarz - Austin TX, US
Scott Johnson - Austin TX, US
Andrew Morten - Austin TX, US

International Classification:

G06F 17/16
G06N 20/00

Abstract:

Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

US Patent:

20190251137, Aug 15, 2019

Filed:

Apr 24, 2019

Appl. No.:

16/392979

Inventors:

- Austin TX, US
Michael Henry - Austin TX, US
Laura Fick - Austin TX, US
Malav Parikh - Austin TX, US
Skylar Skrzyniarz - Austin TX, US
Scott Johnson - Austin TX, US
Andrew Morten - Austin TX, US

International Classification:

G06F 17/16
G06N 20/00

Abstract:

Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

US Patent:

20190188241, Jun 20, 2019

Filed:

Dec 17, 2018

Appl. No.:

16/222277

Inventors:

- Austin TX, US
Michael Henry - Austin TX, US
Laura Fick - Austin TX, US
Malav Parikh - Austin TX, US
Skylar Skrzyniarz - Austin TX, US
Scott Johnson - Austin TX, US
Andrew Morten - Austin TX, US

International Classification:

G06F 17/16
G06N 20/00

Abstract:

Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.