Swapnil Y. Dhumal - Brentwood MO, US Lawrence P. Flannery - Warrenton MO, US Thomas A. Torack - Oakland MO, US John A. Pitney - St. Peters MO, US
Assignee:
MEMC ELECTRONIC MATERIALS, INC. - St. Peters MO
International Classification:
H01L 21/20
US Classification:
438479, 438458, 257E2109
Abstract:
Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.
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