Lawrence R Fraley

US Patent:

6992896, Jan 31, 2006

Filed:

Sep 15, 2003

Appl. No.:

10/661616

Inventors:

Lawrence R. Fraley - Jupiter FL, US
Voya Markovich - Endwell NY, US

Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY

International Classification:

H05K 7/06
H05K 7/20
H01L 23/34

US Classification:

361719, 361780, 257706, 257707, 257723, 257777, 438109, 438122

Abstract:

A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e. g. , an ASIC chip, is solder bonded to the carrier while the second chip, e. g. , a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

US Patent:

7023707, Apr 4, 2006

Filed:

Mar 24, 2003

Appl. No.:

10/394135

Inventors:

Lawrence R. Fraley - Endicott NY, US
Voya R. Markovich - Endwell NY, US

Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY

International Classification:

H05K 7/06
H05K 7/20
H01L 23/34
H01L 23/58

US Classification:

361783, 361719, 361780, 361794, 257704, 257706, 257707, 257723

Abstract:

An information handling system, e. g. , computer, server or mainframe, which includes a multi-chip electronic package utilizing an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities of the final system product.

US Patent:

7035113, Apr 25, 2006

Filed:

Mar 24, 2003

Appl. No.:

10/394107

Inventors:

Lawrence R. Fraley - Endicott NY, US
Voya R. Markovich - Endwell NY, US

Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY

International Classification:

H05K 7/06
H05K 7/20
H01L 23/34
H01L 23/58

US Classification:

361783, 361719, 361780, 361794, 257704, 257706, 257707, 257723, 438122, 438125

Abstract:

A multi-chip electronic package which utilizes an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities.

US Patent:

7161810, Jan 9, 2007

Filed:

Sep 30, 2005

Appl. No.:

11/238960

Inventors:

Lawrence R. Fraley - Jupiter FL, US
Voya Markovich - Endwell NY, US

Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY

International Classification:

H05K 7/06
H05K 7/20
H01L 23/34

US Classification:

361719, 361780, 361810, 257706, 257707, 257723, 257777, 438109, 438122

Abstract:

A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e. g. , an ASIC chip, is solder bonded to the carrier while the second chip, e. g. , a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

US Patent:

7665207, Feb 23, 2010

Filed:

Jun 19, 2006

Appl. No.:

11/455183

Inventors:

Lawrence R. Fraley - Jupiter FL, US
Voya Markovich - Endwell NY, US

Assignee:

Endicott Interconnect Technologies, Inc. - Endicott NY

International Classification:

H05K 3/30

US Classification:

29834, 29840, 29846, 174260, 257706, 361719, 438109

Abstract:

A method of making a multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e. g. , an ASIC chip, is solder bonded to the carrier while the second chip, e. g. , a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

US Patent:

D2813556, Nov 12, 1985

Filed:

Oct 3, 1983

Appl. No.:

6/538723

Inventors:

Lawrence R. Fraley - West Boxford MA
Arnold E. Westlund - Winchester KY

Assignee:

GTE Products Corporation - Stamford CT

US Classification:

D26 2

US Patent:

42291615, Oct 21, 1980

Filed:

Jan 2, 1979

Appl. No.:

6/000033

Inventors:

Andre C. Bouchard - Peabody MA
Lawrence R. Fraley - Ipswich MA

Assignee:

GTE Products Corporation - Stamford CT

International Classification:

F21K 502

US Classification:

431362

Abstract:

An electrically-activated photoflash lamp which includes a thin member (e. g. a mica disk) therein located between the lamp's combustible shreds and primer material. The disk prevents the shreds from contacting the primer material and any portions of the lamp's electrical conductors which have access to the interior of the envelope. A method of making the lamp is also provided.

US Patent:

41613880, Jul 17, 1979

Filed:

Mar 17, 1977

Appl. No.:

5/778395

Inventors:

Andre C. Bouchard - Peabody MA
Lawrence R. Fraley - Ipswich MA

Assignee:

GTE Sylvania Incorporated - Stamford CT

International Classification:

F21K 502
F21L 2500
F21K 200

US Classification:

431359

Abstract:

A flashlamp signal device which includes an illumination means for providing a prolonged, visible signal after actuation of each of the device's flashlamps. The illumination means may be in the form of a phosphor coating within the device or on an adjacent, movable panel, or the phosphor may be impregnated within the light-transmitting housing or support structure of the device.