Lawrence E Larson

US Patent:

8056274, Nov 15, 2011

Filed:

Apr 7, 2009

Appl. No.:

12/419902

Inventors:

Joshua James - Studio City CA, US
Fred Northup - Seattle WA, US
Lawrence Scott Larson - Seattle WA, US
Jeremy Kolenbrander - Brighton CO, US
James Ladtkow - Brighton CO, US

Assignee:

Rain Globes LLC - Seattle WA

International Classification:

G09F 19/00
G09F 19/08
E03B 9/20
B05B 17/08
B05B 1/00
B05B 1/26
B05B 15/00
F21S 8/00
A63H 3/52
A63H 13/02

US Classification:

40406, 40409, 40410, 40412, 40422, 40439, 239 16, 239 17, 239 18, 239 20, 239211, 239548, 239556, 239558, 446267, 446296, 472 65

Abstract:

A dioramic apparatus includes a vessel having an inferior portion and a superior portion. The vessel includes a shell and defines an interior space. The interior space is partially filled by a liquid medium. At least one dioramic scene is disposed in the interior space. A reservoir is in fluid communication with the interior space. The reservoir includes a flow plate defining at least one liquid intake and at least one liquid output port. The at least one liquid intake is configured and arranged for receiving at least a portion of the liquid medium from the interior space when the dioramic apparatus is at least partially inverted. The at least one liquid output port is configured and arranged to output at least a portion of the liquid medium from the reservoir when the vessel is placed in an upright position.

US Patent:

56292414, May 13, 1997

Filed:

Jul 7, 1995

Appl. No.:

8/499800

Inventors:

Mehran Matloubian - Encino CA
Perry A. Macdonald - Culver City CA
David B. Rensch - Thousand Oaks CA
Lawrence E. Larson - Bethesda MD

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H01L 2160

US Classification:

438125

Abstract:

A microwave/millimeter wave circuit structure supports discrete circuit elements by flip-chip mounting to an interconnection network on a low cost non-ceramic and non-semiconductor dielectric substrate, preferably Duroid. The necessary precise alignment of the circuit elements with contact pads on the substrate network required for the high operating frequencies is facilitated by oxidizing the interconnection network, but providing the contact pads from a non-oxidizable material to establish a preferential solder bump wetting for the pads. Alternately, the contact bumps on the flip-chips can be precisely positioned through corresponding openings in a passivation layer over the interconnection network. For thin circuit substrates that are too soft for successful flip-chip mounting, stiffening substrates are laminated to the circuit substrates. In a self-contained antenna application in which two of the circuit substrates are laminated together, with an antenna on one side and circuitry on the other side, a metallic ground plane between the substrates also serves a stiffening function.

US Patent:

54895499, Feb 6, 1996

Filed:

Apr 14, 1994

Appl. No.:

8/223496

Inventors:

Thomas C. Hasenberg - Agoura Hills CA
April S. Brown - Westlake Village CA
Lawrence E. Larson - Santa Monica CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H01L 2120

US Classification:

437133

Abstract:

High speed Group III-Sb materials are n-doped in a molecular beam epitaxy process by forming a superlattice with n-doped strained layers of a Group III-V compound upon Group III-Sb base layers. The base layers have lower conduction band energy levels than the strained layers, and allow doping electrons from the strained layers to flow into the base layers. The base layers preferably comprise Al. sub. x Ga. sub. 1-x Sb, while the strained layers preferably comprise a binary or ternary compound such as Al. sub. y Ga. sub. 1-y As having a single Group V component, where x and y are each from 0 to 1. The strained layers can be n-doped with silicon or tin, which would produce p-type doping if added directly to the base layers.

US Patent:

51721970, Dec 15, 1992

Filed:

Dec 20, 1991

Appl. No.:

7/812875

Inventors:

Loi D. Nguyen - Agoura Hills CA
Michael J. Delaney - Thousand Oaks CA
Lawrence E. Larson - Santa Monica CA
Umesh K. Mishra - Cary NC

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H01L 2980

US Classification:

357 22

Abstract:

A channel layer, donor layer, Schottky layer, and cap layer are formed on a substrate. A source and drain are formed on the cap layer. A gate is formed on the cap layer, or at the bottom of a recess which is formed through the cap layer and partially extends into the Schottky layer. The donor and Schottky layers are formed of a semiconductive material which includes an oxidizable component such as aluminum. A passivation or stop layer of a lattice-matched, non-oxidizable material is formed underlying the source, drain, and gate, and sealingly overlying the donor layer. The stop layer may be formed between the Schottky layer and the donor layer, or constitute a superlattice in combination with the Schottky layer consisting of alternating stop and Schottky sublayers. Alternatively, the stop layer may sealingly overlie the Schottky layer, and further constitute the cap layer.

US Patent:

46821490, Jul 21, 1987

Filed:

Oct 2, 1985

Appl. No.:

6/782777

Inventors:

Lawrence E. Larson - Los Angeles CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H03M 172

US Classification:

340347DA

Abstract:

A high resolution pipelined digital-to-analog converter is disclosed having at least one switching circuit for conveying charge to at least one conversion capacitor upon receipt of a digital signal during the first half of a clock cycle. Additional switching circuits are provided for transferring the charge from the conversion capacitors to a feedback capacitor during the second half of the clock cycle. Also provided is a circuit for discharging an analog output from, and preventing the charging of, the feedback capacitor during the first half of a succeeding clock cycle. In a preferred embodiment, the pipelined digital-to-analog converter comprises a first plurality of electrical circuits having at least one feedback capacitor and a plurality of conversion capacitors adapted for accepting digital and analog inputs, wherein the ratio of the feedback capacitance to each of the conversion capacitances is substantially independent of the resolution of the converter. A second plurality of electrical circuits is also provided which is operable to delay at least one bit of the digital signal to one of the first plurality of electrical circuits. The digital-to-analog converter is operable to allow the number of n-bit digital words converted by the converter to be independent of the resolution of the converter.

US Patent:

48720100, Oct 3, 1989

Filed:

Feb 8, 1988

Appl. No.:

7/153750

Inventors:

Lawrence E. Larson - Los Angeles CA
Joseph F. Jensen - Malibu CA
Robert H. Walden - Westlake Village CA
Adele E. Schmitz - Newbury Park CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H03M 118

US Classification:

341134

Abstract:

An analog-to-digital converter 10 employs a series of comparators 12, 14, 16 and 18. Each comparator includes at least one inverter consisting of a CMOS transistor pair including a P-channel transistor 22 and N-channel transistor 24. The threshold levels of the transistors 22, 24 are modified using focused ion beam implantation techniques to provide the comparators with monotonically increasing transistion levels.

US Patent:

51461170, Sep 8, 1992

Filed:

Apr 1, 1991

Appl. No.:

7/678489

Inventors:

Lawrence E. Larson - Santa Monica CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H03K 19094

US Classification:

307465

Abstract:

A plurality of field effect transistors (FETS) (Q. sub. 0 A to Q. sub. n-1 A, and Q. sub. 0 B to Q. sub. n-1 B) are arranged in a structure (10) to normally perform a first logic function such as NAND. Selectively implanting the channel region (38) of at least one of the FETs (30) with sufficient ions of a predetermined ion species such that the respective FET (30) maintains a constant logic state (constantly turned ON or OFF) for all logical values of applied gate voltage converts the structure (10) to perform a second logic function such as NOR. Alternatively, one of the logic states may be "stuck high" (constant logical high output) or "stuck low" (constant logical low output). The channel implants are substantially undetectable, rendering the structure (10) highly resistant to reverse engineering.

US Patent:

51210894, Jun 9, 1992

Filed:

Nov 1, 1990

Appl. No.:

7/608139

Inventors:

Lawrence E. Larson - Santa Monica CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H01P 110

US Classification:

333107

Abstract:

A miniature electrostatically actuated switch and process for fabricating it in which the switch is operable to connect and disconnect one or more transmission lines laid down on a dielectric substrate of an integrated circuit wafer. The switch is fabricated on the integrated circuit wafer using integrated circuit fabrication processes including thin films of conductive materials and photoresist and selective removal of these films. the switch includes a rotating switch blade which rotates about a hub formed on the dielectric substrate under the influence of electrostatic fields created by control pads and other switch elements formed on the dielectric substrate, whereupon a microwave signal can be switchably transmitted along the transmission line formed on the substrate.