Lei Chen

US Patent:

6339453, Jan 15, 2002

Filed:

Jul 26, 1999

Appl. No.:

09/359792

Inventors:

Lei Chen - Milpitas CA
Hiroyuki Chimoto - Yokohama, JP

Assignee:

Kabushiki Kaisha Toshiba - Kawasaki

International Classification:

H04N 5445

US Classification:

348589, 348563, 348569, 348600

Abstract:

A television system includes a television and an external media module. The television includes a television control unit capable of generating a control signal, apparatus for receiving a video signal, a media controller for generating a graphics signal, and a display unit for displaying either the video signal or a combined video and graphics signal. The external media module, external to the television, is connectable via an interface with the media controller, and performs a graphics on-screen display application in accordance with the television control signal.

US Patent:

6587999, Jul 1, 2003

Filed:

May 15, 2001

Appl. No.:

09/859149

Inventors:

Lei Chen - Mountain View CA
Sandeep Bhutani - Towson MD

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 945

US Classification:

716 6, 716 5, 716 10, 716 17, 716 18

Abstract:

A method of modeling delays in an integrated circuit design is disclosed that may be used to reduce the computation time of path delays in an integrated circuit design. A method of modeling delays in an integrated circuit design includes the steps of receiving as input a description of an integrated circuit design; identifying at least one small net in the integrated circuit design from the description; approximating an effective capacitance of the at least one small net by the total capacitance; and approximating an interconnect delay of the at least one small net by zero.

US Patent:

6989551, Jan 24, 2006

Filed:

Nov 2, 2001

Appl. No.:

10/053004

Inventors:

Allen Gunther - Hillsboro OR, US
Lei Chen - Portland OR, US
Mao Du - Portland OR, US
Mike Rowlandson - Portland OR, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H01L 23/58

US Classification:

257 48

Abstract:

In one embodiment of the invention, a test structure far testing the sufficiency of tunnel opening sizes in a non-volatile memory cell includes N write paths aligned substantially in parallel, each of the write paths beings individually programmable and M floating gates, each of the floating gates overlapping each of the multiple write paths to form a N column-by-M row array of Intersecting areas. An N column-by-M row array of tunnel openings is formed in the intersecting areas and between the floating gates and write paths, with the tunnel openings in each array column being of a same size and the tunnel openings in each array row being of different sizes. A read path coupled to the M floating gates is operable to detect a programmed write path if the tunnel openings formed over the programmed write path are of sufficient size to successfully couple the M floating gates to the programmed write path.

US Patent:

7571302, Aug 4, 2009

Filed:

Feb 4, 2005

Appl. No.:

11/050454

Inventors:

Lei Chen - Austin TX, US
David Albonesi - Ithaca NY, US
Steve Dropsho - CH1010, Lausanne, CH

International Classification:

G06F 9/00

US Classification:

712217

Abstract:

A data dependence table in RAM relates physical register addresses to instructions such that for each instruction, the registers on whose data the instruction depends are identified. The table is updated for each instruction added to the pipeline. For a branch instruction, the table identifies the registers relevant to the branch instruction for branch prediction.

US Patent:

8027800, Sep 27, 2011

Filed:

Jun 24, 2008

Appl. No.:

12/145407

Inventors:

Ramez Nachman - Santa Clara CA, US
Lei Chen - Cupertino CA, US
Tao Yu - Campbell CA, US

Assignee:

QUALCOMM MEMS Technologies, Inc. - San Diego CA

International Classification:

G01R 31/00

US Classification:

702117, 702 64, 702 81

Abstract:

In some embodiments, each interferometric modulator has a stiction threshold voltage. If a voltage above the stiction threshold voltage is applied to the interferometric modulator, the interferometric modulator enters a stiction state permanently, i. e. , becomes “stuck,” and the interferometric modulator becomes inoperable. Disclosed are apparatuses, methods and computer-readable media for testing a panel of interferometric modulators. A ramped voltage waveform is applied to a plurality of interferometric modulators of the panel. In response to applying the ramped voltage, the stiction threshold voltage is identified. At or above this voltage, the number of stuck interferometric modulators in the panel reaches or exceeds a first threshold number, for example, 50% of the total number of the interferometric modulators constituting the panel. The embodiments can be used to establish stiction benchmark for panel manufacturing processes, to collect data for generating statistical distribution, etc.

US Patent:

8086831, Dec 27, 2011

Filed:

Feb 1, 2008

Appl. No.:

12/024241

Inventors:

Lei Chen - Austin TX, US
Lixin Zhang - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/35
G06F 9/355

US Classification:

712240, 712239

Abstract:

In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.

US Patent:

8255631, Aug 28, 2012

Filed:

Feb 1, 2008

Appl. No.:

12/024389

Inventors:

Lei Chen - Austin TX, US
Lixin Zhang - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 9/00

US Classification:

711137, 711E12004, 712225

Abstract:

A method, processor, and data processing system for implementing a framework for priority-based scheduling and throttling of prefetching operations. A prefetch engine (PE) assigns a priority to a first prefetch stream, indicating a relative priority for scheduling prefetch operations of the first prefetch stream. The PE monitors activity within the data processing system and dynamically updates the priority of the first prefetch stream based on the activity (or lack thereof). Low priority streams may be discarded. The PE also schedules prefetching in a priority-based scheduling sequence that corresponds to the priority currently assigned to the scheduled active streams. When there are no prefetches within a prefetch queue, the PE triggers the active streams to provide prefetches for issuing. The PE determines when to throttle prefetching, based on the current usage level of resources relevant to completing the prefetch.

US Patent:

8285765, Oct 9, 2012

Filed:

Dec 11, 2006

Appl. No.:

11/608907

Inventors:

Lei Chen - Austin TX, US
Hung C. Ngo - Austin TX, US
Kevin J. Nowka - Georgetown TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/38

US Classification:

708207

Abstract:

A system and method for implementing arithmetic logic unit (ALU) support for value-based control dependence sequences. According to a first embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value, which is the larger value. According to a second embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value. The third value is a fourth value, if the carry-out signal designates the first value as the larger value or the third value is a fifth value, if the carry-out signal designates the second value as the larger value.