Lei J Chen

US Patent:

6989551, Jan 24, 2006

Filed:

Nov 2, 2001

Appl. No.:

10/053004

Inventors:

Allen Gunther - Hillsboro OR, US
Lei Chen - Portland OR, US
Mao Du - Portland OR, US
Mike Rowlandson - Portland OR, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H01L 23/58

US Classification:

257 48

Abstract:

In one embodiment of the invention, a test structure far testing the sufficiency of tunnel opening sizes in a non-volatile memory cell includes N write paths aligned substantially in parallel, each of the write paths beings individually programmable and M floating gates, each of the floating gates overlapping each of the multiple write paths to form a N column-by-M row array of Intersecting areas. An N column-by-M row array of tunnel openings is formed in the intersecting areas and between the floating gates and write paths, with the tunnel openings in each array column being of a same size and the tunnel openings in each array row being of different sizes. A read path coupled to the M floating gates is operable to detect a programmed write path if the tunnel openings formed over the programmed write path are of sufficient size to successfully couple the M floating gates to the programmed write path.