Leslie A Avery

US Patent:

6501632, Dec 31, 2002

Filed:

Aug 4, 2000

Appl. No.:

09/632414

Inventors:

Leslie Ronald Avery - Flemington NJ
Christian Cornelius Russ - Princeton NJ

Assignee:

Sarnoff Corporation - Princeton NJ

International Classification:

H02H 322

US Classification:

361111, 361 56, 327313, 327534

Abstract:

Apparatus for providing electrostatic discharge protection having an nMOS transistor with bias simultaneously applied to the gate and the p-well of the nMOS transistor. A bias circuit is fabricated using a plurality of the Zener diodes. The double bias allows for a relatively high gate voltage to be applied to the nMOS transistor enabling the nMOS transistor to be biased to optimum conditions for bipolar snapback.

US Patent:

6529359, Mar 4, 2003

Filed:

Aug 4, 2000

Appl. No.:

09/632226

Inventors:

Koen Gerard Maria Verhaege - Gistel, BE
Leslie Ronald Avery - Flemington NJ

Assignee:

Sarnoff Corporation - Princeton NJ

International Classification:

H02H 300

US Classification:

361100

Abstract:

A circuit for the protection of an output driver NMOS transistor during EOS/ESD stress includes an output driver NMOS transistor and an output driver PMOS transistor connected in series between a Vss line and a Vdd line with the gates of the output driver transistors being connected together. An I/O pad is connected to the junction of the output driver transistors. A pre-driver NMOS transistor and a pre-driver PMOS transistor are connected in series between the Vss line and the Vdd line with the gates of the out-put driver transistors being connected together with the output of the pre-driver transistors being connected to the gates of the output driver transistors. A gate clamp is connected between the Vss line, the I/O pad the junction between the pre-driver transistors and the gate of the output driver NMOS transistor. An ESD clamp is connected between the I/O pad, the Vss line and the gate clamp. The gate clamp may comprise a trigger circuit and an inverter circuit with the trigger circuit being either a capacitor and a resistor, or a resistor, MOS transistor and a Zener diode.

US Patent:

6577480, Jun 10, 2003

Filed:

Jul 27, 2000

Appl. No.:

09/626853

Inventors:

Leslie Ronald Avery - Flemington NJ
Peter Daryl Gardner - Lubec ME

Assignee:

Sarnoff Corporation - Princeton NJ

International Classification:

H02H 900

US Classification:

361 56, 361111

Abstract:

An electrostatic protection (ESD) circuit for an integrated circuit (IC) includes a string of a plurality of diodes connected between a Vss line and a Vdd line. A first PMOS transistor and a first NMOS transistor are connected in series between the Vdd line and the string of diodes. The first PMOS transistor has a gate connected between two of the diodes of the string, and the NMOS transistor has a gate connected to the Vdd line. A second PMOS transistor and a second NMOS transistor are connected in series between the Vss line and the Vdd line with the PMOS transistor having a gate connected to the junction between the first PMOS transistor and the first NMOS transistor and the second NMOS transistor having a gate connected to the Vdd line. A clamp NMOS transistor is connected between the Vss line and the Vdd line and has a gate connected to the junction between the second PMOS transistor and the second NMOS transistor. A diode may be connected between the Vdd line and the second PMOS transistor.

US Patent:

6594132, Jul 15, 2003

Filed:

Jul 26, 2000

Appl. No.:

09/625804

Inventors:

Leslie Ronald Avery - Flemington NJ

Assignee:

Sarnoff Corporation - Princeton NJ

International Classification:

H02H 322

US Classification:

361111

Abstract:

An exemplary embodiment of the invention eliminates the common P-Well in a stacked SCR structure by providing isolated P-Wells. This embodiment is particularly advantageous in electrostatic protection devices (ESD) formed from a plurality of silicon controlled rectifiers connected in series. The isolated P-Wells are formed, in part, by a high voltage CMOS process incorporating a relatively heavily doped retrograde buried N layer that enables the formation of junction isolated P-Wells surrounded by an N-Well. The complete isolation of the P-Well prevents the normal P-Well to P substrate short, enabling more effective triggering of stacked SCRs. Advantages of implementing isolated P-Wells over a common P-Well in a stacked SCR electrostatic protection device, include faster triggering, lower current triggering, and a reduction in the number of triggering structures required. These advantages are desirable for deep sub-micron ESD protection structures.

US Patent:

6618233, Sep 9, 2003

Filed:

Jul 27, 2000

Appl. No.:

09/627090

Inventors:

Christian Cornelius Russ - Princeton NJ
Koen Gerard Maria Verhaege - Gistel, BE
Leslie Ronald Avery - Flemington NJ

Assignee:

Sarnoff Corporation - Princeton NJ

International Classification:

H02H 322

US Classification:

361111, 257355, 257173, 257360, 361 56

Abstract:

An ESD protection circuit includes a SCR and a switching means, such as a MOS transistor connected to the SCR so that the SCR is turned on by the switching means to allow an ESD pulse to pass from a Pad line to a grounded VSS line and thereby dissipate the ESD pulse. The SCR is connected between the Pad line and the VSS line. One MOS switching means is connected between the Pad line and the SCR and has a gate which is connected to a VDD line which maintains the switch in open condition during normal VDD bias conditions. An ESD pulse applied to the Pad line, the switch is preconditioned in ON mode allowing the SCR to be predisposed to conduction to allow the ESD pulse to flow to the VSS line.

US Patent:

6791122, Sep 14, 2004

Filed:

Nov 5, 2001

Appl. No.:

10/007833

Inventors:

Leslie R. Avery - Flemington NJ
Christian C. Russ - Princeton NJ
Koen G. M. Verhaege - Gistel, BE
Markus P. J. Mergens - Plainsboro NJ
John Armer - Middlesex NJ

Assignee:

Sarnoff Corporation - Princeton NJ
Sarnoff Europe - Gistel

International Classification:

H01L 2974

US Classification:

257173, 257355, 257358, 257359, 257360, 257363, 257373, 257374

Abstract:

A silicon controlled rectifier electrostatic discharge protection circuit with external on-chip triggering and compact internal dimensions for fast triggering. The ESD protection circuit includes a silicon controlled rectifier (SCR) having an anode coupled to the protected circuitry and a cathode coupled to ground, where the cathode has at least one high-doped region. At least one trigger-tap is disposed proximate to the at least one high-doped region and an external on-chip triggering device is coupled to the trigger-tap and the protected circuitry.

US Patent:

20020117748, Aug 29, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/796302

Inventors:

Leslie Avery - Flemington NJ, US
Robert Amantea - Manalapan NJ, US
Lawrence Goodman - Plainsboro NJ, US

International Classification:

H01L023/34

US Classification:

257/723000, 257/724000

Abstract:

An integrated circuit system includes a substrate of an electrical insulating material having a surface. Mounted on the surface of the substrate is an IC, a semiconductor piece having therein a circuit, such as a microprocessor, having a plurality of functional blocks. Also mounted on the substrate are a plurality of power supply chips. Each of the power supply chips is connected through conductors and vias in the substrate to a separate functional block on the IC semiconductor piece. Each of the power supply chips forms part of a circuit, such as a DC-DC converter, which is capable of reducing a voltage supplied thereto to a lower voltage suitable for the particular functional block to which the particular power supply chip is connected. Thus, a single relatively large voltage fed to the power supply chips through conductors on the substrate is reduced by each power supply chip to a lower voltage suitable for the particular functional block of the IC semiconductor piece.

US Patent:

56150741, Mar 25, 1997

Filed:

Aug 17, 1995

Appl. No.:

8/516072

Inventors:

Leslie R. Avery - Flemington NJ

Assignee:

David Sarnoff Research Center, Inc. - Princeton NJ

International Classification:

H02H 906

US Classification:

361 56

Abstract:

An ESD protection circuit includes a portion for protecting a pair of power lines and a portion for protecting an input/output pin. The power line protection portion includes at least three SCRs electrically connected in series between the power lines. A zener diode is electrically connected between a gate of the SCR at one end of the series and the negative power line, and a resistor is electrically connected between the gate of the one SCR and the positive power line. The gates of the other SCRs in the series are electrically connected to the negative power line or to their own cathode. The I/O pin protection portion includes a plurality of SCRs connected in series between the power lines with the I/O pin being connected between the SCR at one end of the series and the next adjacent SCR in the series. A separate zener diode is electrically connected between the gate of the SCR at the one end of the series and the gate of the next adjacent SCR and the negative power line. A separate resistor is connected between the gate of the SCR at the one end of the series and the next adjacent SCR and the positive power line.