Lester David Sanders

US Patent:

6871172, Mar 22, 2005

Filed:

Jan 22, 2001

Appl. No.:

09/767323

Inventors:

Lester Sanders - Albuquerque NM, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F017/50

US Classification:

703 14, 703 2, 703 18, 703 22, 716 2, 716 4

Abstract:

Method and apparatus for determining power dissipation for an integrated circuit using computer simulation is described. More particularly, the integrated circuit is divided into cells, and one or more nodes are identified within each of the cells. A capacitive load value is ascribed to each of the nodes, and code is generated to track charges in state of each of the nodes. A total for changes in state for each node is divided by simulation time to determine a switching frequency. Using switching frequency, capacitive load and source voltage, dynamic power dissipation for each node may be determined. By summing dynamic power dissipation for all said nodes, total dynamic power dissipation may be determined.

US Patent:

7068080, Jun 27, 2006

Filed:

Jan 17, 2003

Appl. No.:

10/347054

Inventors:

Lester S. Sanders - Albuquerque NM, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 17/00

US Classification:

327 99, 327544, 327141, 326 93

Abstract:

Method and apparatus for reducing power consumption within a logic device is described. A logic device comprises a clock gate and a flip-flop. The clock gate includes a clock enable terminal and a clock terminal. The flip-flop includes an input terminal, an output terminal, and a configuration terminal. The flip-flop is coupled to the clock gate. The flip-flop is configurable to trigger on at least one of a rising edge and a falling edge of a clock signal. The clock gate controllably gates the clock signal coupled to the clock terminal.

US Patent:

7142008, Nov 28, 2006

Filed:

Dec 9, 2003

Appl. No.:

10/732508

Inventors:

Lester S. Sanders - Albuquerque NM, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173
G06F 1/04

US Classification:

326 38, 326 47, 327298

Abstract:

According to one example embodiment, a complex, programmable logic device (CPLD-type) has logic blocks and Input/Output (I/O) pads interconnected via a programmable interconnect array. A dedicated logic block is directly coupled to I/O pads, which provides external access to the dedicated logic block without traversing the programmable interconnect array. The dedicated logic block may include a clock divider module for providing a divided clock to the CPLD.

US Patent:

7272542, Sep 18, 2007

Filed:

Apr 30, 2001

Appl. No.:

09/847032

Inventors:

Lester S. Sanders - Albuquerque NM, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 5/00

US Classification:

703 2, 703 14, 716 2, 716 16

Abstract:

The present invention allows a designer to easily re-target the design optimized for the device of one integrated circuit vendor to the device of another vendor. The designer can start with a set of post-routed boolean equations optimized for a certain target integrated circuit. The present invention allows the automatic generation of a synthesizable, editable, and simulatable HDL description. The designer may edit the HDL code. Another target may be selected. Design optimization and placement and routing can be performed for the new target.

US Patent:

7505887, Mar 17, 2009

Filed:

Jan 31, 2006

Appl. No.:

11/344475

Inventors:

John A. Canaris - Albuquerque NM, US
Jorge Ernesto Carrillo - San Jose CA, US
Lester S. Sanders - Albuquerque NM, US
Yong Zhu - Albuquerque NM, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 14, 703 13, 703 15, 716 4, 716 5

Abstract:

Methods and systems for building a simulation for verifying a design block, including efficient coordination of the control and validation of the operation of a first and second bus of the design block, with the first bus being an interface bus of a processor. An interface description is determined for a bus functional model of the interface bus of the processor. The interface description includes a synchronization bus for coordinating the bus functional model and a hardware description language (HDL) testbench. A hardware specification is generated that couples the first bus of the design block with the interface description, and couples the HDL testbench with the second bus of the design block and with the synchronization bus of the interface description. The simulation for verifying the design block is automatically generated from the bus functional model and the hardware specification.

US Patent:

6536017, Mar 18, 2003

Filed:

May 24, 2001

Appl. No.:

09/865906

Inventors:

Lester S. Sanders - Albuquerque NM

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 3, 716 10

Abstract:

A system and method for translating a report file to a constraints file is provided. A circuit design is initially generated to be implemented on a logic device and a report file corresponding to the logic device is created. To transfer the circuit design to a different logic device, a constraints file generator analyzes the report file to determine characteristics of the logic device. A compatibility logic identifies a compatible device to the logic device based on the characteristics. A constraints file is then generated in accordance with the compatible logic device such that the circuit design can be re-targeted to the compatible device.